Subversion Repositories tinyvliw8

library IEEE;
use IEEE.std_logic_1164.all;
 
entity lib_tb_clock32kHz is
	port (
		signal clk   : out std_logic;
		signal rst_n : out std_logic
	);
end lib_tb_clock32kHz;
 
architecture beh of lib_tb_clock32kHz is
 
component rstCtrl is
	port (
		rstIn_n  : in std_logic;
		clk      : in std_logic;
		pol      : in std_logic;  -- polarity of 1st clock edge (0 => falling)
 
		rstOut_n : out std_logic
	);
end component;
 
	signal internal_clk_s : std_logic;
	signal rst_n_s        : std_logic;
 
	signal rstAsync_n_s   : std_logic;
 
begin
 
	rst_delay_i: rstCtrl
	port map (
		rstIn_n  => rstAsync_n_s,
		clk      => internal_clk_s,
		pol      => '0',
 
		rstOut_n => rst_n_s
	);
 
	clk <= internal_clk_s;
	rst_n <= rst_n_s;
 
	gen_clk : process
	begin
		internal_clk_s <= '1';
		wait for 15000 ns;
		internal_clk_s <= '0';
		wait for 15000 ns;
	end process;
 
	gen_rst : process
	begin
		wait for 1000 ns;
		rstAsync_n_s <= '0';
		wait for 32000 ns;
		rstAsync_n_s <= '1';
 
		wait;
	end process;
 
end beh;