Subversion Repositories tinyvliw8

-------------------------------------------------------------------------------
--
-- Design:  tinyVLIW8 soft-core processor
-- Author:  Oliver Stecklina <stecklina@ihp-microelectronics.com>
-- Date:    24.10.2013 
-- File:    sysArch_tb.vhd
--
-------------------------------------------------------------------------------
--
-- Description : System architecture testbench. Using a ROM initialized by
--               ihex file to simplify system tests.
--
-------------------------------------------------------------------------------
--
--    Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
--
-- This code is free software. It is licensed under the EUPL, Version 1.1
-- or - as soon they will be approved by the European Commission - subsequent
-- versions of the EUPL (the "License").
-- You may redistribute this code and/or modify it under the terms of this
-- License.
-- You may not use this work except in compliance with the License.
-- You may obtain a copy of the License at:
--
-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" basis,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity sysArch_tb is
end sysArch_tb;
 
architecture beh of sysArch_tb is
 
component sysArch
	port (
		-- clock input
		clk           : in std_logic;
 
		-- instruction bus
		instMemAddr   : out std_logic_vector(10 downto 0);
		instMemDataIn : in  std_logic_vector(31 downto 0);
		instMemEn_n   : out std_logic;
 
		-- data bus
		dataMemAddr    : out std_logic_vector(7 downto 0);
		dataMemDataIn  : in  std_logic_vector(7 downto 0);
		dataMemDataOut : out std_logic_vector(7 downto 0);
		dataMemEn_n    : out std_logic;
		dataMemWr_n    : out std_logic;
 
		ioAddr    : out std_logic_vector(7 downto 0);
		ioDataIn  : in  std_logic_vector(7 downto 0);
		ioDataOut : out std_logic_vector(7 downto 0);
		ioWrEn_n  : out std_logic;
		ioRdEn_n  : out std_logic;
 
		-- interrupt handling
		irqLine        : in  std_logic;
		irqLineAck     : out std_logic;
 
		-- general purpose IO
		gpio_in  : in  std_logic_vector(7 downto 0);
		gpio_out : out	std_logic_vector(7 downto 0);
		gpio_dir : out	std_logic_vector(7 downto 0);
 
		spi_clk  : OUT STD_LOGIC;	-- SPI clock
		spi_cs   : OUT STD_LOGIC;	-- SPI slave select, active level configurable
		spi_mosi : OUT STD_LOGIC;	-- SPI master output, slave input
		spi_miso : IN  STD_LOGIC; 	-- SPI master input, slave output
 
		stall_n      : in std_logic;
		stalled_n    : out std_logic;
 
		-- reset input
		rst_n        : in std_logic
	);
end component;
 
component lib_tb_clock32kHz is
	port (
		signal clk   : out std_logic;
		signal rst_n : out std_logic
	);
end component;
 
component dataMem
	PORT (
		address  	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		data  		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		inclock		: IN STD_LOGIC;
		outclock		: IN STD_LOGIC;
		wren  		: IN STD_LOGIC;
		q  			: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component dataMem;
 
component lib_tb_rom32bit is
	generic ( fileName : string );
	port (
		signal addr    : in std_logic_vector(10 downto 0);
		signal dataOut : out std_logic_vector(31 downto 0);
		signal en_n    : in std_logic
	);
end component;
 
component gendelay
	generic (n: integer := 1);
	port (
		a_in	: in	std_logic;
		a_out	: out	std_logic
	);
end component;
 
	signal clk_s       : std_logic;
 
	signal dataAddr_s  : std_logic_vector(7 downto 0);
	signal dataIn_s    : std_logic_vector(7 downto 0);
	signal dataOut_s   : std_logic_vector(7 downto 0);
	signal dataEn_n_s  : std_logic;
	signal dataEnDly_n_s  : std_logic;
	signal dataWr_n_s  : std_logic;
	signal dataWr_s  : std_logic;
 
	signal instAddr_s  : std_logic_vector(10 downto 0);
	signal instData_s  : std_logic_vector(31 downto 0);
	signal instEn_n_s  : std_logic;
 
	signal gpio_in_s   : std_logic_vector(7 downto 0);
	signal gpio_out_s  : std_logic_vector(7 downto 0);
	signal gpio_dir_s  : std_logic_vector(7 downto 0);
 
	signal stall_n_s   : std_logic := '1';
	signal stalled_n_s : std_logic;
 
	signal ioAddr_s     : std_logic_vector(7 downto 0) := (others => '0');
	signal ioDataIn_s   : std_logic_vector(7 downto 0) := (others => '0');
	signal ioDataOut_s  : std_logic_vector(7 downto 0);
	signal ioWrEn_n_s   : std_logic                    := '1';
	signal ioRdEn_n_s   : std_logic                    := '1';
 
	signal irqLine_s    : std_logic;
	signal irqLineAck_s : std_logic                    := '0';
 
	signal spiClk_s  : std_logic;
	signal spiCs_s   : std_logic;
	signal spiMosi_s : std_logic;
	signal spiMiso_s : std_logic := '0';
 
	signal dataInClk_s   : std_logic;
	signal dataOutClk_s  : std_logic;
 
	signal rst_n_s     : std_logic                     := '1';
 
begin
 
	sysArch_i : sysArch
	port map(
		clk           => clk_s,
 
		-- instruction bus
		instMemAddr   => instAddr_s,
		instMemDataIn => instData_s,
		instMemEn_n   => instEn_n_s,
 
		-- data bus
		dataMemAddr    => dataAddr_s,
		dataMemDataIn  => dataIn_s,
		dataMemDataOut => dataOut_s,
		dataMemEn_n    => dataEn_n_s,
		dataMemWr_n    => dataWr_n_s,
 
		ioAddr         => ioAddr_s,
		ioDataIn       => ioDataIn_s,
		ioDataOut      => ioDataOut_s,
		ioWrEn_n       => ioWrEn_n_s,
		ioRdEn_n       => ioRdEn_n_s,
 
		irqLine        => irqLine_s,
		irqLineAck     => irqLineAck_s,
 
		-- general purpose IO
		gpio_in  => gpio_in_s,
		gpio_out => gpio_out_s,
		gpio_dir => gpio_dir_s,
 
		spi_clk  => spiClk_s,
		spi_cs   => spiCs_s,
		spi_mosi => spiMosi_s,
		spi_miso => spiMiso_s,
 
		stall_n        => stall_n_s,
		stalled_n      => stalled_n_s,
 
		rst_n         => rst_n_s
	);
 
	tb_clock32kHz_i: lib_tb_clock32kHz
	port map (
		clk     => clk_s,
		rst_n   => rst_n_s
	);
 
	tb_rom32bit_i: lib_tb_rom32bit
	generic map ( fileName => "../opencores/tinyvliw8/tinyvliw8/trunk/programs/timerIrq.ihex" )
	port map (
		addr    => instAddr_s,
		dataOut => instData_s,
		en_n    => instEn_n_s
	);
 
	dataMem_i : dataMem
	port map (
		address   => dataAddr_s,
		data      => dataOut_s,
		inclock   => dataInClk_s,
		outclock  => dataOutClk_s,
		wren      => dataWr_s,
		q         => dataIn_s
	);
 
	dataWr_s <= not(dataWr_n_s);
 
	dataMemOutClk_delay_i: gendelay
		generic map (n => 5)
		port map (
			a_in	=> dataEn_n_s,
			a_out	=> dataEnDly_n_s
		);
 
	dataInClk_s <= '1' when (dataEn_n_s = '0' and dataEnDly_n_s = '1' and dataWr_n_s = '1') or
	                        (dataEn_n_s = '0' and dataEnDly_n_s = '0' and dataWr_n_s = '0') else
	               '0';
	dataOutClk_s <= not(dataInClk_s);
 
end beh;