URL
https://opencores.org/ocsvn/tm1637/tm1637/trunk
Subversion Repositories tm1637
[/] [tm1637/] [trunk/] [hdl/] [intel_qp/] [dec_counter/] [db/] [prev_cmp_tm1637.qmsg] - Rev 3
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615485200855 ""}{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615485200856 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 18:53:20 2021 " "Processing started: Thu Mar 11 18:53:20 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615485200856 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615485200856 ""}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off tm1637 -c tm1637 " "Command: quartus_map --read_settings_files=on --write_settings_files=off tm1637 -c tm1637" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615485200856 ""}{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1615485201093 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tm1637_external_connect.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tm1637_external_connect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tm1637_external_connect-Behavioral " "Found design unit 1: tm1637_external_connect-Behavioral" { } { { "tm1637_external_connect.vhd" "" { Text "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_external_connect.vhd" 23 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615485212436 ""} { "Info" "ISGN_ENTITY_NAME" "1 tm1637_external_connect " "Found entity 1: tm1637_external_connect" { } { { "tm1637_external_connect.vhd" "" { Text "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_external_connect.vhd" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615485212436 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615485212436 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tm1637_toplevel.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tm1637_toplevel.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tm1637_toplevel-Behavioral " "Found design unit 1: tm1637_toplevel-Behavioral" { } { { "tm1637_toplevel.vhd" "" { Text "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_toplevel.vhd" 17 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615485212437 ""} { "Info" "ISGN_ENTITY_NAME" "1 tm1637_toplevel " "Found entity 1: tm1637_toplevel" { } { { "tm1637_toplevel.vhd" "" { Text "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_toplevel.vhd" 10 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615485212437 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615485212437 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tm1637_decimal_count.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tm1637_decimal_count.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tm1637_decimal_count-behavioral " "Found design unit 1: tm1637_decimal_count-behavioral" { } { { "tm1637_decimal_count.vhd" "" { Text "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_decimal_count.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615485212438 ""} { "Info" "ISGN_ENTITY_NAME" "1 tm1637_decimal_count " "Found entity 1: tm1637_decimal_count" { } { { "tm1637_decimal_count.vhd" "" { Text "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_decimal_count.vhd" 8 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615485212438 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615485212438 ""}{ "Info" "ISGN_START_ELABORATION_TOP" "tm1637_toplevel " "Elaborating entity \"tm1637_toplevel\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1615485212494 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tm1637_decimal_count tm1637_decimal_count:dc " "Elaborating entity \"tm1637_decimal_count\" for hierarchy \"tm1637_decimal_count:dc\"" { } { { "tm1637_toplevel.vhd" "dc" { Text "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_toplevel.vhd" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1615485212522 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tm1637_external_connect tm1637_external_connect:tec " "Elaborating entity \"tm1637_external_connect\" for hierarchy \"tm1637_external_connect:tec\"" { } { { "tm1637_toplevel.vhd" "tec" { Text "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_toplevel.vhd" 72 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1615485212532 ""}{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1615485213904 ""}{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1615485214747 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1615485214747 ""}{ "Info" "ICUT_CUT_TM_SUMMARY" "369 " "Implemented 369 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1615485214876 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1615485214876 ""} { "Info" "ICUT_CUT_TM_LCELLS" "366 " "Implemented 366 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1615485214876 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1615485214876 ""}{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "624 " "Peak virtual memory: 624 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615485214886 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 18:53:34 2021 " "Processing ended: Thu Mar 11 18:53:34 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615485214886 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615485214886 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:31 " "Total CPU time (on all processors): 00:00:31" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615485214886 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1615485214886 ""}{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1615485216154 ""}{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615485216155 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 18:53:35 2021 " "Processing started: Thu Mar 11 18:53:35 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615485216155 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1615485216155 ""}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off tm1637 -c tm1637 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off tm1637 -c tm1637" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1615485216155 ""}{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1615485216291 ""}{ "Info" "0" "" "Project = tm1637" { } { } 0 0 "Project = tm1637" 0 0 "Fitter" 0 0 1615485216294 ""}{ "Info" "0" "" "Revision = tm1637" { } { } 0 0 "Revision = tm1637" 0 0 "Fitter" 0 0 1615485216295 ""}{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1615485216359 ""}{ "Info" "IMPP_MPP_USER_DEVICE" "tm1637 EP4CE6E22C8 " "Selected device EP4CE6E22C8 for design \"tm1637\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1615485216367 ""}{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615485216410 ""}{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615485216411 ""}{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1615485216571 ""}{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1615485216586 ""}{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10E22C8 " "Device EP4CE10E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615485216723 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C8 " "Device EP4CE15E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615485216723 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C8 " "Device EP4CE22E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615485216723 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1615485216723 ""}{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 6 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6" { } { { "/home/mongoq/projects/fpga/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/mongoq/projects/fpga/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/" { { 0 { 0 ""} 0 607 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615485216737 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 8 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8" { } { { "/home/mongoq/projects/fpga/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/mongoq/projects/fpga/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/" { { 0 { 0 ""} 0 609 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615485216737 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 12 " "Pin ~ALTERA_DCLK~ is reserved at location 12" { } { { "/home/mongoq/projects/fpga/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/mongoq/projects/fpga/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/" { { 0 { 0 ""} 0 611 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615485216737 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 13 " "Pin ~ALTERA_DATA0~ is reserved at location 13" { } { { "/home/mongoq/projects/fpga/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/mongoq/projects/fpga/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/" { { 0 { 0 ""} 0 613 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615485216737 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ 101 " "Pin ~ALTERA_nCEO~ is reserved at location 101" { } { { "/home/mongoq/projects/fpga/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/mongoq/projects/fpga/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/" { { 0 { 0 ""} 0 615 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1615485216737 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1615485216737 ""}{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1615485216743 ""}{ "Info" "ISTA_SDC_FOUND" "tm1637.sdc " "Reading SDC File: 'tm1637.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1615485217176 ""}{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1615485217185 ""}{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1615485217185 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1615485217185 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 25.000 clk25 " " 25.000 clk25" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1615485217185 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1615485217185 ""}{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk25~input (placed in PIN 25 (CLK3, DIFFCLK_1n)) " "Automatically promoted node clk25~input (placed in PIN 25 (CLK3, DIFFCLK_1n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1615485217275 ""} } { { "tm1637_toplevel.vhd" "" { Text "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_toplevel.vhd" 11 0 0 } } { "temporary_test_loc" "" { Generic "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/" { { 0 { 0 ""} 0 602 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1615485217275 ""}{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1615485217503 ""}{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615485217504 ""}{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615485217504 ""}{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1615485217506 ""}{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1615485217507 ""}{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1615485217508 ""}{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1615485217508 ""}{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1615485217508 ""}{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1615485217535 ""}{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1615485217537 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1615485217537 ""}{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615485217558 ""}{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1615485217572 ""}{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1615485218236 ""}{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615485218358 ""}{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1615485218375 ""}{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1615485218627 ""}{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615485218627 ""}{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1615485218881 ""}{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X11_Y12 X22_Y24 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24" { } { { "loc" "" { Generic "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} { { 12 { 0 ""} 11 12 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1615485219548 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available deviceresources" 0 0 "Fitter" 0 -1 1615485219548 ""}{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1615485219633 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1615485219633 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1615485219633 ""}{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615485219634 ""}{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.11 " "Total time spent on timing analysis during the Fitter is 0.11 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1615485219773 ""}{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1615485219781 ""}{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1615485220007 ""}{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1615485220007 ""}{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1615485220311 ""}{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615485220693 ""}{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/output_files/tm1637.fit.smsg " "Generated suppressed messages file /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/output_files/tm1637.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1615485220879 ""}{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "876 " "Peak virtual memory: 876 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615485221213 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 18:53:41 2021 " "Processing ended: Thu Mar 11 18:53:41 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615485221213 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615485221213 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615485221213 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1615485221213 ""}{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1615485222607 ""}{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615485222608 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 18:53:42 2021 " "Processing started: Thu Mar 11 18:53:42 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615485222608 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1615485222608 ""}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off tm1637 -c tm1637 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off tm1637 -c tm1637" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1615485222608 ""}{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1615485223155 ""}{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1615485223172 ""}{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "550 " "Peak virtual memory: 550 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615485223288 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 18:53:43 2021 " "Processing ended: Thu Mar 11 18:53:43 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615485223288 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615485223288 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615485223288 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1615485223288 ""}{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1615485223585 ""}{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1615485224505 ""}{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615485224506 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 18:53:44 2021 " "Processing started: Thu Mar 11 18:53:44 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615485224506 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1615485224506 ""}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta tm1637 -c tm1637 " "Command: quartus_sta tm1637 -c tm1637" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1615485224506 ""}{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1615485224556 ""}{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1615485224650 ""}{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1615485224694 ""}{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1615485224694 ""}{ "Info" "ISTA_SDC_FOUND" "tm1637.sdc " "Reading SDC File: 'tm1637.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1615485224869 ""}{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1615485224877 ""}{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1615485224881 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "setup 11.116 " "Worst-case setup slack is 11.116" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485224894 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485224894 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 11.116 0.000 clk25 " " 11.116 0.000 clk25 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485224894 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1615485224894 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.454 " "Worst-case hold slack is 0.454" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485224896 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485224896 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.454 0.000 clk25 " " 0.454 0.000 clk25 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485224896 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1615485224896 ""}{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1615485224897 ""}{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1615485224898 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.281 " "Worst-case minimum pulse width slack is 0.281" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485224899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485224899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.281 0.000 clk25 " " 0.281 0.000 clk25 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485224899 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1615485224899 ""}{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1615485224933 ""}{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1615485224964 ""}{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1615485225277 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.076 " "Worst-case setup slack is 12.076" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225371 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225371 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 12.076 0.000 clk25 " " 12.076 0.000 clk25 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225371 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1615485225371 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.402 " "Worst-case hold slack is 0.402" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225373 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225373 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.402 0.000 clk25 " " 0.402 0.000 clk25 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225373 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1615485225373 ""}{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1615485225375 ""}{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1615485225376 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.272 " "Worst-case minimum pulse width slack is 0.272" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.272 0.000 clk25 " " 0.272 0.000 clk25 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225377 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1615485225377 ""}{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1615485225403 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "setup 18.963 " "Worst-case setup slack is 18.963" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225530 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225530 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 18.963 0.000 clk25 " " 18.963 0.000 clk25 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225530 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1615485225530 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.187 " "Worst-case hold slack is 0.187" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.187 0.000 clk25 " " 0.187 0.000 clk25 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225534 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1615485225534 ""}{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1615485225536 ""}{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1615485225538 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.500 " "Worst-case minimum pulse width slack is 0.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225539 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225539 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.500 0.000 clk25 " " 0.500 0.000 clk25 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1615485225539 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1615485225539 ""}{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1615485225917 ""}{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1615485225917 ""}{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "622 " "Peak virtual memory: 622 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615485225950 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 18:53:45 2021 " "Processing ended: Thu Mar 11 18:53:45 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615485225950 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615485225950 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615485225950 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1615485225950 ""}{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1615485227198 ""}{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615485227198 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 11 18:53:47 2021 " "Processing started: Thu Mar 11 18:53:47 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615485227198 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1615485227198 ""}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off tm1637 -c tm1637 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off tm1637 -c tm1637" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1615485227199 ""}{ "Info" "IWSC_DONE_HDL_GENERATION" "tm1637_8_1200mv_85c_slow.vho /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/ simulation " "Generated file tm1637_8_1200mv_85c_slow.vho in folder \"/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1615485227657 ""}{ "Info" "IWSC_DONE_HDL_GENERATION" "tm1637_8_1200mv_0c_slow.vho /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/ simulation " "Generated file tm1637_8_1200mv_0c_slow.vho in folder \"/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1615485227729 ""}{ "Info" "IWSC_DONE_HDL_GENERATION" "tm1637_min_1200mv_0c_fast.vho /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/ simulation " "Generated file tm1637_min_1200mv_0c_fast.vho in folder \"/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1615485227800 ""}{ "Info" "IWSC_DONE_HDL_GENERATION" "tm1637.vho /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/ simulation " "Generated file tm1637.vho in folder \"/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1615485227873 ""}{ "Info" "IWSC_DONE_HDL_GENERATION" "tm1637_8_1200mv_85c_vhd_slow.sdo /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/ simulation " "Generated file tm1637_8_1200mv_85c_vhd_slow.sdo in folder \"/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1615485227929 ""}{ "Info" "IWSC_DONE_HDL_GENERATION" "tm1637_8_1200mv_0c_vhd_slow.sdo /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/ simulation " "Generated file tm1637_8_1200mv_0c_vhd_slow.sdo in folder \"/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1615485227984 ""}{ "Info" "IWSC_DONE_HDL_GENERATION" "tm1637_min_1200mv_0c_vhd_fast.sdo /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/ simulation " "Generated file tm1637_min_1200mv_0c_vhd_fast.sdo in folder \"/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1615485228039 ""}{ "Info" "IWSC_DONE_HDL_GENERATION" "tm1637_vhd.sdo /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/ simulation " "Generated file tm1637_vhd.sdo in folder \"/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1615485228098 ""}{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "807 " "Peak virtual memory: 807 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615485228126 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 11 18:53:48 2021 " "Processing ended: Thu Mar 11 18:53:48 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615485228126 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615485228126 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615485228126 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1615485228126 ""}{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 2 s " "Quartus Prime Full Compilation was successful. 0 errors, 2 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1615485228267 ""}