Subversion Repositories tm1637

{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615649018573 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615649018574 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 13 16:23:38 2021 " "Processing started: Sat Mar 13 16:23:38 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615649018574 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615649018574 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off tm1637 -c tm1637 " "Command: quartus_map --read_settings_files=on --write_settings_files=off tm1637 -c tm1637" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615649018574 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1615649018803 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tm1637_external_connect.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tm1637_external_connect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tm1637_external_connect-Behavioral " "Found design unit 1: tm1637_external_connect-Behavioral" {  } { { "tm1637_external_connect.vhd" "" { Text "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_external_connect.vhd" 23 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615649030685 ""} { "Info" "ISGN_ENTITY_NAME" "1 tm1637_external_connect " "Found entity 1: tm1637_external_connect" {  } { { "tm1637_external_connect.vhd" "" { Text "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_external_connect.vhd" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615649030685 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615649030685 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tm1637_toplevel.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tm1637_toplevel.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tm1637_toplevel-Behavioral " "Found design unit 1: tm1637_toplevel-Behavioral" {  } { { "tm1637_toplevel.vhd" "" { Text "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_toplevel.vhd" 17 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615649030687 ""} { "Info" "ISGN_ENTITY_NAME" "1 tm1637_toplevel " "Found entity 1: tm1637_toplevel" {  } { { "tm1637_toplevel.vhd" "" { Text "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_toplevel.vhd" 10 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615649030687 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615649030687 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tm1637_decimal_count.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tm1637_decimal_count.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tm1637_decimal_count-behavioral " "Found design unit 1: tm1637_decimal_count-behavioral" {  } { { "tm1637_decimal_count.vhd" "" { Text "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_decimal_count.vhd" 14 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615649030687 ""} { "Info" "ISGN_ENTITY_NAME" "1 tm1637_decimal_count " "Found entity 1: tm1637_decimal_count" {  } { { "tm1637_decimal_count.vhd" "" { Text "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_decimal_count.vhd" 8 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615649030687 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615649030687 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "tm1637_toplevel " "Elaborating entity \"tm1637_toplevel\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1615649030744 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tm1637_decimal_count tm1637_decimal_count:dc " "Elaborating entity \"tm1637_decimal_count\" for hierarchy \"tm1637_decimal_count:dc\"" {  } { { "tm1637_toplevel.vhd" "dc" { Text "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_toplevel.vhd" 61 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1615649030746 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tm1637_external_connect tm1637_external_connect:tec " "Elaborating entity \"tm1637_external_connect\" for hierarchy \"tm1637_external_connect:tec\"" {  } { { "tm1637_toplevel.vhd" "tec" { Text "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_toplevel.vhd" 72 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1615649030747 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1615649032098 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1615649032920 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1615649032920 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "369 " "Implemented 369 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1615649033058 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1615649033058 ""} { "Info" "ICUT_CUT_TM_LCELLS" "366 " "Implemented 366 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1615649033058 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1615649033058 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "623 " "Peak virtual memory: 623 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615649033066 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 13 16:23:53 2021 " "Processing ended: Sat Mar 13 16:23:53 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615649033066 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615649033066 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:33 " "Total CPU time (on all processors): 00:00:33" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615649033066 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1615649033066 ""}