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https://opencores.org/ocsvn/tm1637/tm1637/trunk
Subversion Repositories tm1637
[/] [tm1637/] [trunk/] [hdl/] [intel_qp/] [dec_counter/] [output_files/] [tm1637.eda.rpt] - Rev 3
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EDA Netlist Writer report for tm1637Sat Mar 13 16:24:06 2021Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. EDA Netlist Writer Summary3. Simulation Settings4. Simulation Generated Files5. EDA Netlist Writer Messages----------------; Legal Notice ;----------------Copyright (C) 2020 Intel Corporation. All rights reserved.Your use of Intel Corporation's design tools, logic functionsand other software and tools, and any partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Intel Program LicenseSubscription Agreement, the Intel Quartus Prime License Agreement,the Intel FPGA IP License Agreement, or other applicable licenseagreement, including, without limitation, that your use is forthe sole purpose of programming logic devices manufactured byIntel and sold by Intel or its authorized distributors. Pleaserefer to the applicable agreement for further details, athttps://fpgasoftware.intel.com/eula.+-------------------------------------------------------------------+; EDA Netlist Writer Summary ;+---------------------------+---------------------------------------+; EDA Netlist Writer Status ; Successful - Sat Mar 13 16:24:06 2021 ;; Revision Name ; tm1637 ;; Top-level Entity Name ; tm1637_toplevel ;; Family ; Cyclone IV E ;; Simulation Files Creation ; Successful ;+---------------------------+---------------------------------------++----------------------------------------------------------------------------------------------------------------------------+; Simulation Settings ;+---------------------------------------------------------------------------------------------------+------------------------+; Option ; Setting ;+---------------------------------------------------------------------------------------------------+------------------------+; Tool Name ; ModelSim-Altera (VHDL) ;; Generate functional simulation netlist ; Off ;; Time scale ; 1 ps ;; Truncate long hierarchy paths ; Off ;; Map illegal HDL characters ; Off ;; Flatten buses into individual nodes ; Off ;; Maintain hierarchy ; Off ;; Bring out device-wide set/reset signals as ports ; Off ;; Enable glitch filtering ; Off ;; Do not write top level VHDL entity ; Off ;; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;; Architecture name in VHDL output netlist ; structure ;; Generate third-party EDA tool command script for RTL functional simulation ; Off ;; Generate third-party EDA tool command script for gate-level simulation ; Off ;+---------------------------------------------------------------------------------------------------+------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Simulation Generated Files ;+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Generated Files ;+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_8_1200mv_85c_slow.vho ;; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_8_1200mv_0c_slow.vho ;; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_min_1200mv_0c_fast.vho ;; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637.vho ;; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_8_1200mv_85c_vhd_slow.sdo ;; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_8_1200mv_0c_vhd_slow.sdo ;; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_min_1200mv_0c_vhd_fast.sdo ;; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/tm1637_vhd.sdo ;+---------------------------------------------------------------------------------------------------------------------------------------------------------------------++-----------------------------+; EDA Netlist Writer Messages ;+-----------------------------+Info: *******************************************************************Info: Running Quartus Prime EDA Netlist WriterInfo: Version 20.1.0 Build 711 06/05/2020 SJ Lite EditionInfo: Processing started: Sat Mar 13 16:24:05 2021Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off tm1637 -c tm1637Info (204019): Generated file tm1637_8_1200mv_85c_slow.vho in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file tm1637_8_1200mv_0c_slow.vho in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file tm1637_min_1200mv_0c_fast.vho in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file tm1637.vho in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file tm1637_8_1200mv_85c_vhd_slow.sdo in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file tm1637_8_1200mv_0c_vhd_slow.sdo in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file tm1637_min_1200mv_0c_vhd_fast.sdo in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file tm1637_vhd.sdo in folder "/home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/simulation/modelsim/" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warningsInfo: Peak virtual memory: 807 megabytesInfo: Processing ended: Sat Mar 13 16:24:06 2021Info: Elapsed time: 00:00:01Info: Total CPU time (on all processors): 00:00:01