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Subversion Repositories tm1637
[/] [tm1637/] [trunk/] [hdl/] [intel_qp/] [dec_counter/] [output_files/] [tm1637.fit.rpt] - Rev 3
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Fitter report for tm1637Sat Mar 13 16:23:59 2021Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Fitter Summary3. Fitter Settings4. Parallel Compilation5. Incremental Compilation Preservation Summary6. Incremental Compilation Partition Settings7. Incremental Compilation Placement Preservation8. Pin-Out File9. Fitter Resource Usage Summary10. Fitter Partition Statistics11. Input Pins12. Output Pins13. Dual Purpose and Dedicated Pins14. I/O Bank Usage15. All Package Pins16. I/O Assignment Warnings17. Fitter Resource Utilization by Entity18. Delay Chain Summary19. Pad To Core Delay Chain Fanout20. Control Signals21. Global & Other Fast Signals22. Routing Usage Summary23. LAB Logic Elements24. LAB-wide Signals25. LAB Signals Sourced26. LAB Signals Sourced Out27. LAB Distinct Inputs28. I/O Rules Summary29. I/O Rules Details30. I/O Rules Matrix31. Fitter Device Options32. Operating Settings and Conditions33. Fitter Messages34. Fitter Suppressed Messages----------------; Legal Notice ;----------------Copyright (C) 2020 Intel Corporation. All rights reserved.Your use of Intel Corporation's design tools, logic functionsand other software and tools, and any partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Intel Program LicenseSubscription Agreement, the Intel Quartus Prime License Agreement,the Intel FPGA IP License Agreement, or other applicable licenseagreement, including, without limitation, that your use is forthe sole purpose of programming logic devices manufactured byIntel and sold by Intel or its authorized distributors. Pleaserefer to the applicable agreement for further details, athttps://fpgasoftware.intel.com/eula.+----------------------------------------------------------------------------------+; Fitter Summary ;+------------------------------------+---------------------------------------------+; Fitter Status ; Successful - Sat Mar 13 16:23:59 2021 ;; Quartus Prime Version ; 20.1.0 Build 711 06/05/2020 SJ Lite Edition ;; Revision Name ; tm1637 ;; Top-level Entity Name ; tm1637_toplevel ;; Family ; Cyclone IV E ;; Device ; EP4CE6E22C8 ;; Timing Models ; Final ;; Total logic elements ; 347 / 6,272 ( 6 % ) ;; Total combinational functions ; 332 / 6,272 ( 5 % ) ;; Dedicated logic registers ; 97 / 6,272 ( 2 % ) ;; Total registers ; 97 ;; Total pins ; 3 / 92 ( 3 % ) ;; Total virtual pins ; 0 ;; Total memory bits ; 0 / 276,480 ( 0 % ) ;; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ;; Total PLLs ; 0 / 2 ( 0 % ) ;+------------------------------------+---------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Settings ;+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+; Option ; Setting ; Default Value ;+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+; Device ; EP4CE6E22C8 ; ;; Maximum processors allowed for parallel compilation ; All ; ;; Nominal Core Supply Voltage ; 1.2V ; ;; Minimum Core Junction Temperature ; 0 ; ;; Maximum Core Junction Temperature ; 85 ; ;; Fit Attempts to Skip ; 0 ; 0.0 ;; Use smart compilation ; Off ; Off ;; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;; Enable compact report table ; Off ; Off ;; Auto Merge PLLs ; On ; On ;; Router Timing Optimization Level ; Normal ; Normal ;; Perform Clocking Topology Analysis During Routing ; Off ; Off ;; Placement Effort Multiplier ; 1.0 ; 1.0 ;; Router Effort Multiplier ; 1.0 ; 1.0 ;; Optimize Hold Timing ; All Paths ; All Paths ;; Optimize Multi-Corner Timing ; On ; On ;; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;; SSN Optimization ; Off ; Off ;; Optimize Timing ; Normal compilation ; Normal compilation ;; Optimize Timing for ECOs ; Off ; Off ;; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;; Optimize IOC Register Placement for Timing ; Normal ; Normal ;; Limit to One Fitting Attempt ; Off ; Off ;; Final Placement Optimizations ; Automatically ; Automatically ;; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;; Fitter Initial Placement Seed ; 1 ; 1 ;; Periphery to Core Placement and Routing Optimization ; Off ; Off ;; PCI I/O ; Off ; Off ;; Weak Pull-Up Resistor ; Off ; Off ;; Enable Bus-Hold Circuitry ; Off ; Off ;; Auto Packed Registers ; Auto ; Auto ;; Auto Delay Chains ; On ; On ;; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;; Treat Bidirectional Pin as Output Pin ; Off ; Off ;; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;; Perform Register Duplication for Performance ; Off ; Off ;; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;; Perform Register Retiming for Performance ; Off ; Off ;; Perform Asynchronous Signal Pipelining ; Off ; Off ;; Fitter Effort ; Auto Fit ; Auto Fit ;; Physical Synthesis Effort Level ; Normal ; Normal ;; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;; Auto Register Duplication ; Auto ; Auto ;; Auto Global Clock ; On ; On ;; Auto Global Register Control Signals ; On ; On ;; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;; Synchronizer Identification ; Auto ; Auto ;; Enable Beneficial Skew Optimization ; On ; On ;; Optimize Design for Metastability ; On ; On ;; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;+--------------------------------------------------------------------+---------------------------------------+---------------------------------------++------------------------------------------+; Parallel Compilation ;+----------------------------+-------------+; Processors ; Number ;+----------------------------+-------------+; Number detected on machine ; 4 ;; Maximum allowed ; 2 ;; ; ;; Average used ; 1.03 ;; Maximum used ; 2 ;; ; ;; Usage by Processor ; % Time Used ;; Processor 1 ; 100.0% ;; Processor 2 ; 2.7% ;+----------------------------+-------------++--------------------------------------------------------------------------------------------------+; Incremental Compilation Preservation Summary ;+---------------------+--------------------+----------------------------+--------------------------+; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;+---------------------+--------------------+----------------------------+--------------------------+; Placement (by node) ; ; ; ;; -- Requested ; 0.00 % ( 0 / 447 ) ; 0.00 % ( 0 / 447 ) ; 0.00 % ( 0 / 447 ) ;; -- Achieved ; 0.00 % ( 0 / 447 ) ; 0.00 % ( 0 / 447 ) ; 0.00 % ( 0 / 447 ) ;; ; ; ; ;; Routing (by net) ; ; ; ;; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;+---------------------+--------------------+----------------------------+--------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Incremental Compilation Partition Settings ;+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------++------------------------------------------------------------------------------------------------------------------------------------+; Incremental Compilation Placement Preservation ;+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+; Top ; 0.00 % ( 0 / 437 ) ; N/A ; Source File ; N/A ; ;; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------++--------------+; Pin-Out File ;+--------------+The pin-out file can be found in /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/output_files/tm1637.pin.+-------------------------------------------------------------------+; Fitter Resource Usage Summary ;+---------------------------------------------+---------------------+; Resource ; Usage ;+---------------------------------------------+---------------------+; Total logic elements ; 347 / 6,272 ( 6 % ) ;; -- Combinational with no register ; 250 ;; -- Register only ; 15 ;; -- Combinational with a register ; 82 ;; ; ;; Logic element usage by number of LUT inputs ; ;; -- 4 input functions ; 225 ;; -- 3 input functions ; 33 ;; -- <=2 input functions ; 74 ;; -- Register only ; 15 ;; ; ;; Logic elements by mode ; ;; -- normal mode ; 290 ;; -- arithmetic mode ; 42 ;; ; ;; Total registers* ; 97 / 6,684 ( 1 % ) ;; -- Dedicated logic registers ; 97 / 6,272 ( 2 % ) ;; -- I/O registers ; 0 / 412 ( 0 % ) ;; ; ;; Total LABs: partially or completely used ; 28 / 392 ( 7 % ) ;; Virtual pins ; 0 ;; I/O pins ; 3 / 92 ( 3 % ) ;; -- Clock pins ; 1 / 3 ( 33 % ) ;; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;; ; ;; M9Ks ; 0 / 30 ( 0 % ) ;; Total block memory bits ; 0 / 276,480 ( 0 % ) ;; Total block memory implementation bits ; 0 / 276,480 ( 0 % ) ;; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ;; PLLs ; 0 / 2 ( 0 % ) ;; Global signals ; 1 ;; -- Global clocks ; 1 / 10 ( 10 % ) ;; JTAGs ; 0 / 1 ( 0 % ) ;; CRC blocks ; 0 / 1 ( 0 % ) ;; ASMI blocks ; 0 / 1 ( 0 % ) ;; Oscillator blocks ; 0 / 1 ( 0 % ) ;; Impedance control blocks ; 0 / 4 ( 0 % ) ;; Average interconnect usage (total/H/V) ; 0.7% / 0.6% / 1.0% ;; Peak interconnect usage (total/H/V) ; 3.0% / 2.0% / 4.2% ;; Maximum fan-out ; 97 ;; Highest non-global fan-out ; 56 ;; Total fan-out ; 1440 ;; Average fan-out ; 3.16 ;+---------------------------------------------+---------------------+* Register count does not include registers inside RAM blocks or DSP blocks.+---------------------------------------------------------------------------------------------------+; Fitter Partition Statistics ;+---------------------------------------------+--------------------+--------------------------------+; Statistic ; Top ; hard_block:auto_generated_inst ;+---------------------------------------------+--------------------+--------------------------------+; Difficulty Clustering Region ; Low ; Low ;; ; ; ;; Total logic elements ; 347 / 6272 ( 6 % ) ; 0 / 6272 ( 0 % ) ;; -- Combinational with no register ; 250 ; 0 ;; -- Register only ; 15 ; 0 ;; -- Combinational with a register ; 82 ; 0 ;; ; ; ;; Logic element usage by number of LUT inputs ; ; ;; -- 4 input functions ; 225 ; 0 ;; -- 3 input functions ; 33 ; 0 ;; -- <=2 input functions ; 74 ; 0 ;; -- Register only ; 15 ; 0 ;; ; ; ;; Logic elements by mode ; ; ;; -- normal mode ; 290 ; 0 ;; -- arithmetic mode ; 42 ; 0 ;; ; ; ;; Total registers ; 97 ; 0 ;; -- Dedicated logic registers ; 97 / 6272 ( 2 % ) ; 0 / 6272 ( 0 % ) ;; -- I/O registers ; 0 ; 0 ;; ; ; ;; Total LABs: partially or completely used ; 28 / 392 ( 7 % ) ; 0 / 392 ( 0 % ) ;; ; ; ;; Virtual pins ; 0 ; 0 ;; I/O pins ; 3 ; 0 ;; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ; 0 / 30 ( 0 % ) ;; Total memory bits ; 0 ; 0 ;; Total RAM block bits ; 0 ; 0 ;; Clock control block ; 1 / 12 ( 8 % ) ; 0 / 12 ( 0 % ) ;; ; ; ;; Connections ; ; ;; -- Input Connections ; 0 ; 0 ;; -- Registered Input Connections ; 0 ; 0 ;; -- Output Connections ; 0 ; 0 ;; -- Registered Output Connections ; 0 ; 0 ;; ; ; ;; Internal Connections ; ; ;; -- Total Connections ; 1435 ; 5 ;; -- Registered Connections ; 645 ; 0 ;; ; ; ;; External Connections ; ; ;; -- Top ; 0 ; 0 ;; -- hard_block:auto_generated_inst ; 0 ; 0 ;; ; ; ;; Partition Interface ; ; ;; -- Input Ports ; 1 ; 0 ;; -- Output Ports ; 2 ; 0 ;; -- Bidir Ports ; 0 ; 0 ;; ; ; ;; Registered Ports ; ; ;; -- Registered Input Ports ; 0 ; 0 ;; -- Registered Output Ports ; 0 ; 0 ;; ; ; ;; Port Connectivity ; ; ;; -- Input Ports driven by GND ; 0 ; 0 ;; -- Output Ports driven by GND ; 0 ; 0 ;; -- Input Ports driven by VCC ; 0 ; 0 ;; -- Output Ports driven by VCC ; 0 ; 0 ;; -- Input Ports with no Source ; 0 ; 0 ;; -- Output Ports with no Source ; 0 ; 0 ;; -- Input Ports with no Fanout ; 0 ; 0 ;; -- Output Ports with no Fanout ; 0 ; 0 ;+---------------------------------------------+--------------------+--------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Input Pins ;+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+; clk25 ; 25 ; 2 ; 0 ; 11 ; 21 ; 97 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Output Pins ;+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+; clk ; 132 ; 8 ; 13 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;; dio ; 128 ; 8 ; 16 ; 24 ; 14 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;+------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------++-------------------------------------------------------------------------------------------------------------------------+; Dual Purpose and Dedicated Pins ;+----------+-----------------------------+--------------------------+-------------------------+---------------------------+; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;+----------+-----------------------------+--------------------------+-------------------------+---------------------------+; 6 ; DIFFIO_L1n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;; 8 ; DIFFIO_L2p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;; 9 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;; 12 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;; 13 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;; 14 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;; 21 ; nCE ; - ; - ; Dedicated Programming Pin ;; 92 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;; 94 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;; 96 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;; 97 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;; 97 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;; 101 ; DIFFIO_R3n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;; 132 ; DIFFIO_T10n, DATA2 ; Use as regular IO ; clk ; Dual Purpose Pin ;+----------+-----------------------------+--------------------------+-------------------------+---------------------------++-----------------------------------------------------------+; I/O Bank Usage ;+----------+-----------------+---------------+--------------+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;+----------+-----------------+---------------+--------------+; 1 ; 4 / 11 ( 36 % ) ; 2.5V ; -- ;; 2 ; 1 / 8 ( 13 % ) ; 2.5V ; -- ;; 3 ; 0 / 11 ( 0 % ) ; 2.5V ; -- ;; 4 ; 0 / 14 ( 0 % ) ; 2.5V ; -- ;; 5 ; 0 / 13 ( 0 % ) ; 2.5V ; -- ;; 6 ; 1 / 10 ( 10 % ) ; 2.5V ; -- ;; 7 ; 0 / 13 ( 0 % ) ; 2.5V ; -- ;; 8 ; 2 / 12 ( 17 % ) ; 2.5V ; -- ;+----------+-----------------+---------------+--------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; All Package Pins ;+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; 1 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 3 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 5 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 6 ; 5 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;; 7 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;; 8 ; 7 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;; 9 ; 9 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;; 10 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 11 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 12 ; 15 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;; 13 ; 16 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;; 14 ; 17 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;; 15 ; 18 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;; 16 ; 19 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;; 17 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 18 ; 20 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;; 19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 20 ; 21 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;; 21 ; 22 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;; 22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 23 ; 24 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 24 ; 25 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 25 ; 26 ; 2 ; clk25 ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;; 26 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 28 ; 31 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 29 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 30 ; 34 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 31 ; 36 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;; 32 ; 39 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 33 ; 40 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 34 ; 41 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 35 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 36 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;; 37 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 38 ; 45 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 39 ; 46 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 40 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 41 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 42 ; 52 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 43 ; 53 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 44 ; 54 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 45 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 46 ; 58 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;; 47 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 48 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 49 ; 68 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 50 ; 69 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 51 ; 70 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 52 ; 72 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 53 ; 73 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 54 ; 74 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 55 ; 75 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 56 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 57 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 58 ; 80 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 59 ; 83 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 60 ; 84 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 61 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 62 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 63 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 64 ; 89 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 65 ; 90 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;; 66 ; 93 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 67 ; 94 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 68 ; 96 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 69 ; 97 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 70 ; 98 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 71 ; 99 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 72 ; 100 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 73 ; 102 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 74 ; 103 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 75 ; 104 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 76 ; 106 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 77 ; 107 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 78 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 79 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 80 ; 113 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;; 81 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 82 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 83 ; 117 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 84 ; 118 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 85 ; 119 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 86 ; 120 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 87 ; 121 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 88 ; 125 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 89 ; 126 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 90 ; 127 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 91 ; 128 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 92 ; 129 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;; 93 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 94 ; 130 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;; 95 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 96 ; 131 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;; 97 ; 132 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;; 97 ; 133 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;; 98 ; 136 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 99 ; 137 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 100 ; 138 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 101 ; 139 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;; 102 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 103 ; 140 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 104 ; 141 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 105 ; 142 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;; 106 ; 146 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; 107 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 108 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;; 109 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 110 ; 152 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 111 ; 154 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 112 ; 155 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 113 ; 156 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 114 ; 157 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 115 ; 158 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 116 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 117 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 118 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 119 ; 163 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;; 120 ; 164 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 121 ; 165 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 122 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 123 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 124 ; 173 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 125 ; 174 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 126 ; 175 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 127 ; 176 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 128 ; 177 ; 8 ; dio ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;; 129 ; 178 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 130 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 131 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 132 ; 181 ; 8 ; clk ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;; 133 ; 182 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 134 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 135 ; 185 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 136 ; 187 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;; 137 ; 190 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 138 ; 191 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 139 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 141 ; 195 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 142 ; 201 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 143 ; 202 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; 144 ; 203 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; EPAD ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+Note: Pin directions (input, output or bidir) are based on device operating in user mode.+------------------------------------------+; I/O Assignment Warnings ;+----------+-------------------------------+; Pin Name ; Reason ;+----------+-------------------------------+; clk ; Incomplete set of assignments ;; dio ; Incomplete set of assignments ;; clk25 ; Incomplete set of assignments ;+----------+-------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Resource Utilization by Entity ;+----------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------+-------------------------+--------------+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;+----------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------+-------------------------+--------------+; |tm1637_toplevel ; 347 (0) ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 ; 0 ; 250 (0) ; 15 (0) ; 82 (0) ; |tm1637_toplevel ; tm1637_toplevel ; work ;; |tm1637_decimal_count:dc| ; 50 (50) ; 45 (45) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 9 (9) ; 36 (36) ; |tm1637_toplevel|tm1637_decimal_count:dc ; tm1637_decimal_count ; work ;; |tm1637_external_connect:tec| ; 297 (297) ; 52 (52) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 245 (245) ; 6 (6) ; 46 (46) ; |tm1637_toplevel|tm1637_external_connect:tec ; tm1637_external_connect ; work ;+----------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------+-------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+---------------------------------------------------------------------------------------+; Delay Chain Summary ;+-------+----------+---------------+---------------+-----------------------+-----+------+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;+-------+----------+---------------+---------------+-----------------------+-----+------+; clk ; Output ; -- ; -- ; -- ; -- ; -- ;; dio ; Output ; -- ; -- ; -- ; -- ; -- ;; clk25 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;+-------+----------+---------------+---------------+-----------------------+-----+------++---------------------------------------------------+; Pad To Core Delay Chain Fanout ;+---------------------+-------------------+---------+; Source Pin / Fanout ; Pad To Core Index ; Setting ;+---------------------+-------------------+---------+; clk25 ; ; ;+---------------------+-------------------+---------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Control Signals ;+---------------------------------------------+--------------------+---------+---------------+--------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+---------------------------------------------+--------------------+---------+---------------+--------+----------------------+------------------+---------------------------+; clk25 ; PIN_25 ; 97 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ;; tm1637_decimal_count:dc|LessThan0~3 ; LCCOMB_X23_Y13_N0 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ;; tm1637_decimal_count:dc|ce ; FF_X23_Y13_N1 ; 52 ; Clock enable ; no ; -- ; -- ; -- ;; tm1637_external_connect:tec|dio~45 ; LCCOMB_X18_Y16_N14 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; tm1637_external_connect:tec|dio~en ; FF_X18_Y16_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; tm1637_external_connect:tec|reg_digit0[3]~0 ; LCCOMB_X17_Y16_N4 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;+---------------------------------------------+--------------------+---------+---------------+--------+----------------------+------------------+---------------------------++-----------------------------------------------------------------------------------------------------------------------------------------+; Global & Other Fast Signals ;+-------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+-------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+; clk25 ; PIN_25 ; 97 ; 0 ; Global Clock ; GCLK3 ; -- ;+-------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------++------------------------------------------------+; Routing Usage Summary ;+-----------------------+------------------------+; Routing Resource Type ; Usage ;+-----------------------+------------------------+; Block interconnects ; 398 / 32,401 ( 1 % ) ;; C16 interconnects ; 1 / 1,326 ( < 1 % ) ;; C4 interconnects ; 215 / 21,816 ( < 1 % ) ;; Direct links ; 77 / 32,401 ( < 1 % ) ;; Global clocks ; 1 / 10 ( 10 % ) ;; Local interconnects ; 224 / 10,320 ( 2 % ) ;; R24 interconnects ; 0 / 1,289 ( 0 % ) ;; R4 interconnects ; 170 / 28,186 ( < 1 % ) ;+-----------------------+------------------------++----------------------------------------------------------------------------+; LAB Logic Elements ;+---------------------------------------------+------------------------------+; Number of Logic Elements (Average = 12.39) ; Number of LABs (Total = 28) ;+---------------------------------------------+------------------------------+; 1 ; 4 ;; 2 ; 2 ;; 3 ; 0 ;; 4 ; 0 ;; 5 ; 0 ;; 6 ; 0 ;; 7 ; 0 ;; 8 ; 0 ;; 9 ; 0 ;; 10 ; 0 ;; 11 ; 0 ;; 12 ; 0 ;; 13 ; 1 ;; 14 ; 1 ;; 15 ; 8 ;; 16 ; 12 ;+---------------------------------------------+------------------------------++-------------------------------------------------------------------+; LAB-wide Signals ;+------------------------------------+------------------------------+; LAB-wide Signals (Average = 0.86) ; Number of LABs (Total = 28) ;+------------------------------------+------------------------------+; 1 Clock ; 13 ;; 1 Clock enable ; 11 ;+------------------------------------+------------------------------++-----------------------------------------------------------------------------+; LAB Signals Sourced ;+----------------------------------------------+------------------------------+; Number of Signals Sourced (Average = 15.68) ; Number of LABs (Total = 28) ;+----------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 3 ;; 2 ; 3 ;; 3 ; 0 ;; 4 ; 0 ;; 5 ; 0 ;; 6 ; 0 ;; 7 ; 0 ;; 8 ; 0 ;; 9 ; 0 ;; 10 ; 0 ;; 11 ; 0 ;; 12 ; 0 ;; 13 ; 0 ;; 14 ; 0 ;; 15 ; 7 ;; 16 ; 5 ;; 17 ; 0 ;; 18 ; 2 ;; 19 ; 1 ;; 20 ; 1 ;; 21 ; 1 ;; 22 ; 0 ;; 23 ; 0 ;; 24 ; 0 ;; 25 ; 0 ;; 26 ; 1 ;; 27 ; 0 ;; 28 ; 0 ;; 29 ; 1 ;; 30 ; 0 ;; 31 ; 2 ;; 32 ; 1 ;+----------------------------------------------+------------------------------++--------------------------------------------------------------------------------+; LAB Signals Sourced Out ;+-------------------------------------------------+------------------------------+; Number of Signals Sourced Out (Average = 6.96) ; Number of LABs (Total = 28) ;+-------------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 5 ;; 2 ; 2 ;; 3 ; 0 ;; 4 ; 0 ;; 5 ; 3 ;; 6 ; 2 ;; 7 ; 3 ;; 8 ; 4 ;; 9 ; 2 ;; 10 ; 2 ;; 11 ; 2 ;; 12 ; 0 ;; 13 ; 0 ;; 14 ; 1 ;; 15 ; 0 ;; 16 ; 2 ;+-------------------------------------------------+------------------------------++-----------------------------------------------------------------------------+; LAB Distinct Inputs ;+----------------------------------------------+------------------------------+; Number of Distinct Inputs (Average = 12.75) ; Number of LABs (Total = 28) ;+----------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 1 ;; 2 ; 2 ;; 3 ; 1 ;; 4 ; 3 ;; 5 ; 0 ;; 6 ; 4 ;; 7 ; 0 ;; 8 ; 1 ;; 9 ; 1 ;; 10 ; 0 ;; 11 ; 1 ;; 12 ; 1 ;; 13 ; 0 ;; 14 ; 0 ;; 15 ; 2 ;; 16 ; 0 ;; 17 ; 0 ;; 18 ; 3 ;; 19 ; 1 ;; 20 ; 1 ;; 21 ; 2 ;; 22 ; 0 ;; 23 ; 1 ;; 24 ; 1 ;; 25 ; 1 ;; 26 ; 0 ;; 27 ; 0 ;; 28 ; 0 ;; 29 ; 0 ;; 30 ; 0 ;; 31 ; 0 ;; 32 ; 0 ;; 33 ; 0 ;; 34 ; 0 ;; 35 ; 0 ;; 36 ; 1 ;+----------------------------------------------+------------------------------++------------------------------------------+; I/O Rules Summary ;+----------------------------------+-------+; I/O Rules Statistic ; Total ;+----------------------------------+-------+; Total I/O Rules ; 30 ;; Number of I/O Rules Passed ; 12 ;; Number of I/O Rules Failed ; 0 ;; Number of I/O Rules Unchecked ; 0 ;; Number of I/O Rules Inapplicable ; 18 ;+----------------------------------+-------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; I/O Rules Details ;+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; I/O Rules Matrix ;+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+; Total Pass ; 0 ; 3 ; 3 ; 0 ; 0 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 2 ; 2 ; 0 ; 2 ; 0 ; 0 ; 2 ; 0 ; 3 ; 3 ; 3 ; 0 ; 0 ;; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; Total Inapplicable ; 3 ; 0 ; 0 ; 3 ; 3 ; 0 ; 0 ; 3 ; 3 ; 3 ; 3 ; 3 ; 3 ; 1 ; 3 ; 3 ; 3 ; 1 ; 1 ; 3 ; 1 ; 3 ; 3 ; 1 ; 3 ; 0 ; 0 ; 0 ; 3 ; 3 ;; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; clk ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;; dio ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;; clk25 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------++---------------------------------------------------------------------------------------------+; Fitter Device Options ;+------------------------------------------------------------------+--------------------------+; Option ; Setting ;+------------------------------------------------------------------+--------------------------+; Enable user-supplied start-up clock (CLKUSR) ; Off ;; Enable device-wide reset (DEV_CLRn) ; Off ;; Enable device-wide output enable (DEV_OE) ; Off ;; Enable INIT_DONE output ; Off ;; Configuration scheme ; Active Serial ;; Error detection CRC ; Off ;; Enable open drain on CRC_ERROR pin ; Off ;; Enable input tri-state on active configuration pins in user mode ; Off ;; Configuration Voltage Level ; Auto ;; Force Configuration Voltage Level ; Off ;; nCEO ; As output driving ground ;; Data[0] ; As input tri-stated ;; Data[1]/ASDO ; As input tri-stated ;; Data[7..2] ; Unreserved ;; FLASH_nCE/nCSO ; As input tri-stated ;; Other Active Parallel pins ; Unreserved ;; DCLK ; As output driving ground ;+------------------------------------------------------------------+--------------------------++------------------------------------+; Operating Settings and Conditions ;+---------------------------+--------+; Setting ; Value ;+---------------------------+--------+; Nominal Core Voltage ; 1.20 V ;+---------------------------+--------++-----------------+; Fitter Messages ;+-----------------+Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detectedInfo (119006): Selected device EP4CE6E22C8 for design "tm1637"Info (21077): Low junction temperature is 0 degrees CInfo (21077): High junction temperature is 85 degrees CInfo (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation timeWarning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devicesInfo (176445): Device EP4CE10E22C8 is compatibleInfo (176445): Device EP4CE15E22C8 is compatibleInfo (176445): Device EP4CE22E22C8 is compatibleInfo (169124): Fitter converted 5 user pins into dedicated programming pinsInfo (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 101Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for detailsInfo (332104): Reading SDC File: 'tm1637.sdc'Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirementsInfo (332111): Found 1 clocksInfo (332111): Period Clock NameInfo (332111): ======== ============Info (332111): 25.000 clk25Info (176353): Automatically promoted node clk25~input (placed in PIN 25 (CLK3, DIFFCLK_1n)) File: /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_toplevel.vhd Line: 11Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3Info (176233): Starting register packingInfo (176235): Finished register packingExtra Info (176219): No registers were packed into other blocksInfo (171121): Fitter preparation operations ending: elapsed time is 00:00:01Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.Info (170189): Fitter placement preparation operations beginningInfo (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00Info (170191): Fitter placement operations beginningInfo (170137): Fitter placement was successfulInfo (170192): Fitter placement operations ending: elapsed time is 00:00:00Info (170193): Fitter routing operations beginningInfo (170195): Router estimated average interconnect usage is 0% of the available device resourcesInfo (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.Info (170201): Optimizations that may affect the design's routability were skippedInfo (170200): Optimizations that may affect the design's timing were skippedInfo (170194): Fitter routing operations ending: elapsed time is 00:00:00Info (11888): Total time spent on timing analysis during the Fitter is 0.10 seconds.Info (334003): Started post-fitting delay annotationInfo (334004): Delay annotation completed successfullyInfo (334003): Started post-fitting delay annotationInfo (334004): Delay annotation completed successfullyInfo (11218): Fitter post-fit operations ending: elapsed time is 00:00:00Info (144001): Generated suppressed messages file /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/output_files/tm1637.fit.smsgInfo: Quartus Prime Fitter was successful. 0 errors, 2 warningsInfo: Peak virtual memory: 887 megabytesInfo: Processing ended: Sat Mar 13 16:23:59 2021Info: Elapsed time: 00:00:06Info: Total CPU time (on all processors): 00:00:06+----------------------------+; Fitter Suppressed Messages ;+----------------------------+The suppressed messages can be found in /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/output_files/tm1637.fit.smsg.