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[/] [tm1637/] [trunk/] [hdl/] [intel_qp/] [dec_counter/] [output_files/] [tm1637.map.rpt] - Rev 3
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Analysis & Synthesis report for tm1637Sat Mar 13 16:23:53 2021Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Analysis & Synthesis Summary3. Analysis & Synthesis Settings4. Parallel Compilation5. Analysis & Synthesis Source Files Read6. Analysis & Synthesis Resource Usage Summary7. Analysis & Synthesis Resource Utilization by Entity8. Registers Removed During Synthesis9. General Register Statistics10. Multiplexer Restructuring Statistics (Restructuring Performed)11. Parameter Settings for User Entity Instance: tm1637_decimal_count:dc12. Parameter Settings for User Entity Instance: tm1637_external_connect:tec13. Port Connectivity Checks: "tm1637_external_connect:tec"14. Port Connectivity Checks: "tm1637_decimal_count:dc"15. Post-Synthesis Netlist Statistics for Top Partition16. Elapsed Time Per Partition17. Analysis & Synthesis Messages----------------; Legal Notice ;----------------Copyright (C) 2020 Intel Corporation. All rights reserved.Your use of Intel Corporation's design tools, logic functionsand other software and tools, and any partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Intel Program LicenseSubscription Agreement, the Intel Quartus Prime License Agreement,the Intel FPGA IP License Agreement, or other applicable licenseagreement, including, without limitation, that your use is forthe sole purpose of programming logic devices manufactured byIntel and sold by Intel or its authorized distributors. Pleaserefer to the applicable agreement for further details, athttps://fpgasoftware.intel.com/eula.+----------------------------------------------------------------------------------+; Analysis & Synthesis Summary ;+------------------------------------+---------------------------------------------+; Analysis & Synthesis Status ; Successful - Sat Mar 13 16:23:53 2021 ;; Quartus Prime Version ; 20.1.0 Build 711 06/05/2020 SJ Lite Edition ;; Revision Name ; tm1637 ;; Top-level Entity Name ; tm1637_toplevel ;; Family ; Cyclone IV E ;; Total logic elements ; 364 ;; Total combinational functions ; 332 ;; Dedicated logic registers ; 97 ;; Total registers ; 97 ;; Total pins ; 3 ;; Total virtual pins ; 0 ;; Total memory bits ; 0 ;; Embedded Multiplier 9-bit elements ; 0 ;; Total PLLs ; 0 ;+------------------------------------+---------------------------------------------++------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Settings ;+------------------------------------------------------------------+--------------------+--------------------+; Option ; Setting ; Default Value ;+------------------------------------------------------------------+--------------------+--------------------+; Device ; EP4CE6E22C8 ; ;; Top-level entity name ; tm1637_toplevel ; tm1637 ;; Family name ; Cyclone IV E ; Cyclone V ;; Maximum processors allowed for parallel compilation ; All ; ;; Use smart compilation ; Off ; Off ;; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;; Enable compact report table ; Off ; Off ;; Restructure Multiplexers ; Auto ; Auto ;; Create Debugging Nodes for IP Cores ; Off ; Off ;; Preserve fewer node names ; On ; On ;; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;; Verilog Version ; Verilog_2001 ; Verilog_2001 ;; VHDL Version ; VHDL_1993 ; VHDL_1993 ;; State Machine Processing ; Auto ; Auto ;; Safe State Machine ; Off ; Off ;; Extract Verilog State Machines ; On ; On ;; Extract VHDL State Machines ; On ; On ;; Ignore Verilog initial constructs ; Off ; Off ;; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;; Add Pass-Through Logic to Inferred RAMs ; On ; On ;; Infer RAMs from Raw Logic ; On ; On ;; Parallel Synthesis ; On ; On ;; DSP Block Balancing ; Auto ; Auto ;; NOT Gate Push-Back ; On ; On ;; Power-Up Don't Care ; On ; On ;; Remove Redundant Logic Cells ; Off ; Off ;; Remove Duplicate Registers ; On ; On ;; Ignore CARRY Buffers ; Off ; Off ;; Ignore CASCADE Buffers ; Off ; Off ;; Ignore GLOBAL Buffers ; Off ; Off ;; Ignore ROW GLOBAL Buffers ; Off ; Off ;; Ignore LCELL Buffers ; Off ; Off ;; Ignore SOFT Buffers ; On ; On ;; Limit AHDL Integers to 32 Bits ; Off ; Off ;; Optimization Technique ; Balanced ; Balanced ;; Carry Chain Length ; 70 ; 70 ;; Auto Carry Chains ; On ; On ;; Auto Open-Drain Pins ; On ; On ;; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;; Auto ROM Replacement ; On ; On ;; Auto RAM Replacement ; On ; On ;; Auto DSP Block Replacement ; On ; On ;; Auto Shift Register Replacement ; Auto ; Auto ;; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;; Auto Clock Enable Replacement ; On ; On ;; Strict RAM Replacement ; Off ; Off ;; Allow Synchronous Control Signals ; On ; On ;; Force Use of Synchronous Clear Signals ; Off ; Off ;; Auto RAM Block Balancing ; On ; On ;; Auto RAM to Logic Cell Conversion ; Off ; Off ;; Auto Resource Sharing ; Off ; Off ;; Allow Any RAM Size For Recognition ; Off ; Off ;; Allow Any ROM Size For Recognition ; Off ; Off ;; Allow Any Shift Register Size For Recognition ; Off ; Off ;; Use LogicLock Constraints during Resource Balancing ; On ; On ;; Ignore translate_off and synthesis_off directives ; Off ; Off ;; Timing-Driven Synthesis ; On ; On ;; Report Parameter Settings ; On ; On ;; Report Source Assignments ; On ; On ;; Report Connectivity Checks ; On ; On ;; Ignore Maximum Fan-Out Assignments ; Off ; Off ;; Synchronization Register Chain Length ; 2 ; 2 ;; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;; HDL message level ; Level2 ; Level2 ;; Suppress Register Optimization Related Messages ; Off ; Off ;; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;; Clock MUX Protection ; On ; On ;; Auto Gated Clock Conversion ; Off ; Off ;; Block Design Naming ; Auto ; Auto ;; SDC constraint protection ; Off ; Off ;; Synthesis Effort ; Auto ; Auto ;; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;; Pre-Mapping Resynthesis Optimization ; Off ; Off ;; Analysis & Synthesis Message Level ; Medium ; Medium ;; Disable Register Merging Across Hierarchies ; Auto ; Auto ;; Resource Aware Inference For Block RAM ; On ; On ;+------------------------------------------------------------------+--------------------+--------------------++------------------------------------------+; Parallel Compilation ;+----------------------------+-------------+; Processors ; Number ;+----------------------------+-------------+; Number detected on machine ; 4 ;; Maximum allowed ; 2 ;; ; ;; Average used ; 1.00 ;; Maximum used ; 2 ;; ; ;; Usage by Processor ; % Time Used ;; Processor 1 ; 100.0% ;; Processor 2 ; 0.0% ;+----------------------------+-------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Source Files Read ;+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------+---------+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------+---------+; tm1637_external_connect.vhd ; yes ; User VHDL File ; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_external_connect.vhd ; ;; tm1637_toplevel.vhd ; yes ; User VHDL File ; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_toplevel.vhd ; ;; tm1637_decimal_count.vhd ; yes ; User VHDL File ; /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_decimal_count.vhd ; ;+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------+---------++-----------------------------------------------------------+; Analysis & Synthesis Resource Usage Summary ;+---------------------------------------------+-------------+; Resource ; Usage ;+---------------------------------------------+-------------+; Estimated Total logic elements ; 364 ;; ; ;; Total combinational functions ; 332 ;; Logic element usage by number of LUT inputs ; ;; -- 4 input functions ; 225 ;; -- 3 input functions ; 33 ;; -- <=2 input functions ; 74 ;; ; ;; Logic elements by mode ; ;; -- normal mode ; 290 ;; -- arithmetic mode ; 42 ;; ; ;; Total registers ; 97 ;; -- Dedicated logic registers ; 97 ;; -- I/O registers ; 0 ;; ; ;; I/O pins ; 3 ;; ; ;; Embedded Multiplier 9-bit elements ; 0 ;; ; ;; Maximum fan-out node ; clk25~input ;; Maximum fan-out ; 97 ;; Total fan-out ; 1424 ;; Average fan-out ; 3.27 ;+---------------------------------------------+-------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Resource Utilization by Entity ;+----------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------+-------------------------+--------------+; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;+----------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------+-------------------------+--------------+; |tm1637_toplevel ; 332 (0) ; 97 (0) ; 0 ; 0 ; 0 ; 0 ; 3 ; 0 ; |tm1637_toplevel ; tm1637_toplevel ; work ;; |tm1637_decimal_count:dc| ; 41 (41) ; 45 (45) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |tm1637_toplevel|tm1637_decimal_count:dc ; tm1637_decimal_count ; work ;; |tm1637_external_connect:tec| ; 291 (291) ; 52 (52) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |tm1637_toplevel|tm1637_external_connect:tec ; tm1637_external_connect ; work ;+----------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------+-------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+-----------------------------------------------------------------------------------------+; Registers Removed During Synthesis ;+----------------------------------------+------------------------------------------------+; Register name ; Reason for Removal ;+----------------------------------------+------------------------------------------------+; tm1637_external_connect:tec|ce ; Merged with tm1637_decimal_count:dc|ce ;; tm1637_external_connect:tec|clkdiv[11] ; Merged with tm1637_decimal_count:dc|clkdiv[11] ;; tm1637_external_connect:tec|clkdiv[10] ; Merged with tm1637_decimal_count:dc|clkdiv[10] ;; tm1637_external_connect:tec|clkdiv[9] ; Merged with tm1637_decimal_count:dc|clkdiv[9] ;; tm1637_external_connect:tec|clkdiv[8] ; Merged with tm1637_decimal_count:dc|clkdiv[8] ;; tm1637_external_connect:tec|clkdiv[7] ; Merged with tm1637_decimal_count:dc|clkdiv[7] ;; tm1637_external_connect:tec|clkdiv[6] ; Merged with tm1637_decimal_count:dc|clkdiv[6] ;; tm1637_external_connect:tec|clkdiv[5] ; Merged with tm1637_decimal_count:dc|clkdiv[5] ;; tm1637_external_connect:tec|clkdiv[4] ; Merged with tm1637_decimal_count:dc|clkdiv[4] ;; tm1637_external_connect:tec|clkdiv[3] ; Merged with tm1637_decimal_count:dc|clkdiv[3] ;; tm1637_external_connect:tec|clkdiv[2] ; Merged with tm1637_decimal_count:dc|clkdiv[2] ;; tm1637_external_connect:tec|clkdiv[1] ; Merged with tm1637_decimal_count:dc|clkdiv[1] ;; tm1637_external_connect:tec|clkdiv[0] ; Merged with tm1637_decimal_count:dc|clkdiv[0] ;; Total Number of Removed Registers = 13 ; ;+----------------------------------------+------------------------------------------------++------------------------------------------------------+; General Register Statistics ;+----------------------------------------------+-------+; Statistic ; Value ;+----------------------------------------------+-------+; Total registers ; 97 ;; Number of registers using Synchronous Clear ; 12 ;; Number of registers using Synchronous Load ; 0 ;; Number of registers using Asynchronous Clear ; 0 ;; Number of registers using Asynchronous Load ; 0 ;; Number of registers using Clock Enable ; 68 ;; Number of registers using Preset ; 0 ;+----------------------------------------------+-------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Multiplexer Restructuring Statistics (Restructuring Performed) ;+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------+; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |tm1637_toplevel|tm1637_decimal_count:dc|d10Next[0] ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |tm1637_toplevel|tm1637_decimal_count:dc|d1000Next[1] ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |tm1637_toplevel|tm1637_decimal_count:dc|d100Next[0] ;+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------++----------------------------------------------------------------------+; Parameter Settings for User Entity Instance: tm1637_decimal_count:dc ;+----------------+-------+---------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------+; divider ; 2500 ; Signed Integer ;+----------------+-------+---------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: tm1637_external_connect:tec ;+----------------+-------+-------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------+; divider ; 2500 ; Signed Integer ;+----------------+-------+-------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------+; Port Connectivity Checks: "tm1637_external_connect:tec" ;+------+-------+----------+-------------------------------+; Port ; Type ; Severity ; Details ;+------+-------+----------+-------------------------------+; en ; Input ; Info ; Stuck at VCC ;+------+-------+----------+-------------------------------++-----------------------------------------------------+; Port Connectivity Checks: "tm1637_decimal_count:dc" ;+------+-------+----------+---------------------------+; Port ; Type ; Severity ; Details ;+------+-------+----------+---------------------------+; en ; Input ; Info ; Stuck at VCC ;+------+-------+----------+---------------------------++-----------------------------------------------------+; Post-Synthesis Netlist Statistics for Top Partition ;+-----------------------+-----------------------------+; Type ; Count ;+-----------------------+-----------------------------+; boundary_port ; 3 ;; cycloneiii_ff ; 97 ;; ENA ; 68 ;; SCLR ; 12 ;; plain ; 17 ;; cycloneiii_io_obuf ; 1 ;; cycloneiii_lcell_comb ; 332 ;; arith ; 42 ;; 2 data inputs ; 42 ;; normal ; 290 ;; 1 data inputs ; 3 ;; 2 data inputs ; 29 ;; 3 data inputs ; 33 ;; 4 data inputs ; 225 ;; ; ;; Max LUT depth ; 11.00 ;; Average LUT depth ; 6.26 ;+-----------------------+-----------------------------++-------------------------------+; Elapsed Time Per Partition ;+----------------+--------------+; Partition Name ; Elapsed Time ;+----------------+--------------+; Top ; 00:00:01 ;+----------------+--------------++-------------------------------+; Analysis & Synthesis Messages ;+-------------------------------+Info: *******************************************************************Info: Running Quartus Prime Analysis & SynthesisInfo: Version 20.1.0 Build 711 06/05/2020 SJ Lite EditionInfo: Processing started: Sat Mar 13 16:23:38 2021Info: Command: quartus_map --read_settings_files=on --write_settings_files=off tm1637 -c tm1637Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detectedInfo (12021): Found 2 design units, including 1 entities, in source file tm1637_external_connect.vhdInfo (12022): Found design unit 1: tm1637_external_connect-Behavioral File: /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_external_connect.vhd Line: 23Info (12023): Found entity 1: tm1637_external_connect File: /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_external_connect.vhd Line: 12Info (12021): Found 2 design units, including 1 entities, in source file tm1637_toplevel.vhdInfo (12022): Found design unit 1: tm1637_toplevel-Behavioral File: /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_toplevel.vhd Line: 17Info (12023): Found entity 1: tm1637_toplevel File: /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_toplevel.vhd Line: 10Info (12021): Found 2 design units, including 1 entities, in source file tm1637_decimal_count.vhdInfo (12022): Found design unit 1: tm1637_decimal_count-behavioral File: /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_decimal_count.vhd Line: 14Info (12023): Found entity 1: tm1637_decimal_count File: /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_decimal_count.vhd Line: 8Info (12127): Elaborating entity "tm1637_toplevel" for the top level hierarchyInfo (12128): Elaborating entity "tm1637_decimal_count" for hierarchy "tm1637_decimal_count:dc" File: /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_toplevel.vhd Line: 61Info (12128): Elaborating entity "tm1637_external_connect" for hierarchy "tm1637_external_connect:tec" File: /home/mongoq/projects/fpga/tm1637-opencores/opencores-online-repository/tm1637/trunk/hdl/intel_qp/dec_counter/tm1637_toplevel.vhd Line: 72Info (286030): Timing-Driven Synthesis is runningInfo (16010): Generating hard_block partition "hard_block:auto_generated_inst"Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELLInfo (21057): Implemented 369 device resources after synthesis - the final resource count might be differentInfo (21058): Implemented 1 input pinsInfo (21059): Implemented 2 output pinsInfo (21061): Implemented 366 logic cellsInfo: Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warningsInfo: Peak virtual memory: 623 megabytesInfo: Processing ended: Sat Mar 13 16:23:53 2021Info: Elapsed time: 00:00:15Info: Total CPU time (on all processors): 00:00:33