OpenCores
URL https://opencores.org/ocsvn/tm1637/tm1637/trunk

Subversion Repositories tm1637

[/] [tm1637/] [trunk/] [hdl/] [intel_qp/] [dec_counter/] [simulation/] [modelsim/] [msim_transcript] - Rev 3

Compare with Previous | Blame | View Log

# do tm1637_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
#       vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap work rtl_work 
# Copying /home/mongoq/projects/fpga/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vcom -93 -work work {/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_external_connect.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 20:07:47 on Feb 24,2021
# vcom -reportprogress 300 -93 -work work /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_external_connect.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity tm1637_external_connect
# -- Compiling architecture Behavioral of tm1637_external_connect
# End time: 20:07:47 on Feb 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_toplevel.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 20:07:48 on Feb 24,2021
# vcom -reportprogress 300 -93 -work work /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_toplevel.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity tm1637_toplevel
# -- Compiling architecture Behavioral of tm1637_toplevel
# End time: 20:07:48 on Feb 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {/home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_decimal_count.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 20:07:48 on Feb 24,2021
# vcom -reportprogress 300 -93 -work work /home/mongoq/projects/fpga/tm1637-opencores/tm1637-gama/testing-17.2.21/tm1637-decimal-counter-testing/tm1637_decimal_count.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity tm1637_decimal_count
# -- Compiling architecture behavioral of tm1637_decimal_count
# End time: 20:07:48 on Feb 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# 
# stdin: <EOF>

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.