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// This file is part of TMS1000 CPU
// 
// tms1000_tb.v -  Testbench for the TMS1000 processor
//
// Written By -  Nand Gates (2021)
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the
// Free Software Foundation; either version 2, or (at your option) any
// later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// In other words, you are welcome to use, share and improve this program.
// You are forbidden to forbid anyone else to use, share and improve
// what you give them.   Help stamp out software-hoarding!
 
module tms1000_tb();
   /*AUTOREGINPUT*/
   // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
   reg         clk;                    // To tms1000 of tms1000.v
   tri0 [3:0]  k;                      // To tms1000 of tms1000.v
   reg         reset_n;                // To tms1000 of tms1000.v
   // End of automatics
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire [7:0]  q;                      // From tms1000 of tms1000.v
   wire [10:0] r;                      // From tms1000 of tms1000.v
   // End of automatics
   parameter key_0 = 5'h00;
   parameter key_1 = 5'h01;
   parameter key_2 = 5'h02;
   parameter key_3 = 5'h03;
   parameter key_4 = 5'h04;
   parameter key_5 = 5'h05;
   parameter key_6 = 5'h06;
   parameter key_7 = 5'h07;
   parameter key_8 = 5'h08;
   parameter key_9 = 5'h09;
   parameter key_clk   = 5'h0a;
   parameter key_c     = 5'h0b;
   parameter key_ent   = 5'h0c;
   parameter key_plus  = 5'h0d;
   parameter key_minus = 5'h0e;
   parameter key_mul   = 5'h0f;
   parameter key_div   = 5'h10;
 
   reg         key0     ;
   reg         key1     ;
   reg         key2     ;
   reg         key3     ;
   reg         key4     ;
   reg         key5     ;
   reg         key6     ;
   reg         key7     ;
   reg         key8     ;
   reg         key9     ;
   reg         keyclk   ;
   reg         keyc     ;
   reg         keyent   ;
   reg         keyplus  ;
   reg         keyminus ;
   reg         keymul   ;
   reg         keydiv   ;
   reg         clk_60;
   integer     count;
 
   reg [7:0]   d0, d1, d2, d3, d4, d5, d6, d7, d8;
 
   tms1000 tms1000(/*AUTOINST*/
                   // Outputs
                   .r           (r[10:0]),
                   .q           (q[7:0]),
                   // Inputs
                   .clk         (clk),
                   .reset_n     (reset_n),
                   .k           (k[3:0]));
 
   bufif1 buf0 (k[2], key0    , r[0]); 
   bufif1 buf1 (k[2], key1    , r[1]);
   bufif1 buf2 (k[2], key2    , r[2]);
   bufif1 buf3 (k[2], key3    , r[3]);
   bufif1 buf4 (k[2], key4    , r[4]);
   bufif1 buf5 (k[2], key5    , r[5]);
   bufif1 buf6 (k[2], key6    , r[6]);
 
   bufif1 buf7 (k[1], key7    , r[1]);
   bufif1 buf8 (k[1], key8    , r[2]);
   bufif1 buf9 (k[1], key9    , r[3]);  
 
   bufif1 buf10(k[0], keyclk  , r[0]);
   bufif1 buf11(k[0], keyc    , r[1]);
   bufif1 buf12(k[0], keyent  , r[2]);
   bufif1 buf13(k[0], keyplus , r[3]);
   bufif1 buf14(k[0], keyminus, r[4]);
   bufif1 buf15(k[0], keymul  , r[5]);
   bufif1 buf16(k[0], keydiv  , r[6]);
 
   bufif1 bufclk (k[3], clk_60 , 1'b1); 
 
   task do_key;
      input [4:0] key;
      begin
          case (key)
              key_0     : begin key0    <= 1'b1 ; #25000; key0    <= 1'b0; end 
              key_1     : begin key1    <= 1'b1 ; #25000; key1    <= 1'b0; end 
              key_2     : begin key2    <= 1'b1 ; #25000; key2    <= 1'b0; end 
              key_3     : begin key3    <= 1'b1 ; #25000; key3    <= 1'b0; end 
              key_4     : begin key4    <= 1'b1 ; #25000; key4    <= 1'b0; end 
              key_5     : begin key5    <= 1'b1 ; #25000; key5    <= 1'b0; end 
              key_6     : begin key6    <= 1'b1 ; #25000; key6    <= 1'b0; end 
              key_7     : begin key7    <= 1'b1 ; #25000; key7    <= 1'b0; end 
              key_8     : begin key8    <= 1'b1 ; #25000; key8    <= 1'b0; end 
              key_9     : begin key9    <= 1'b1 ; #25000; key9    <= 1'b0; end 
              key_clk   : begin keyclk  <= 1'b1 ; #25000; keyclk  <= 1'b0; end 
              key_c     : begin keyc    <= 1'b1 ; #25000; keyc    <= 1'b0; end 
              key_ent   : begin keyent  <= 1'b1 ; #25000; keyent  <= 1'b0; end 
              key_plus  : begin keyplus <= 1'b1 ; #25000; keyplus <= 1'b0; end 
              key_minus : begin keyminus<= 1'b1 ; #25000; keyminus<= 1'b0; end 
              key_mul   : begin keymul  <= 1'b1 ; #25000; keymul  <= 1'b0; end 
              key_div   : begin keydiv  <= 1'b1 ; #25000; keydiv  <= 1'b0; end 
          endcase // case(key)
      end
   endtask // do_key
 
   initial begin
      clk = 0;
      key0     = 0;
      key1     = 0;
      key2     = 0;
      key3     = 0;
      key4     = 0;
      key5     = 0;
      key6     = 0;
      key7     = 0;
      key8     = 0;
      key9     = 0;
      keyclk   = 0;
      keyc     = 0;
      keyent   = 0;
      keyplus  = 0;
      keyminus = 0;
      keymul   = 0;
      keydiv   = 0;
      clk_60 = 0;
      count = 0;
 
      d0 = 0;
      d1 = 0;
      d2 = 0;
      d3 = 0;
      d4 = 0;
      d5 = 0;
      d6 = 0;
      d7 = 0;
      d8 = 0;
      reset_n = 0;
      #33 reset_n = 1;
 
/* -----\/----- EXCLUDED -----\/-----
       #28000;
       do_key(key_1);
       #28000;
       do_key(key_2);
       #28000;
       do_key(key_3);
       #28000;
       do_key(key_4);
       #28000;
       do_key(key_5);
       #28000;
       do_key(key_6);
       #28000;
       do_key(key_7);
       #28000;
       do_key(key_8);
       #28000;
       do_key(key_9);
 
 -----/\----- EXCLUDED -----/\----- */
/* -----\/----- EXCLUDED -----\/-----
         do_key(key_2);
         #28000;
         do_key(key_ent);
         #28000;
         do_key(key_4);
         #28000;
         do_key(/-*key_minus key_plus*-/ key_mul);
        #80000;
        $display("Xreg_0 = %h",tms1000_tb.tms1000.ram.Xreg_0[63:0]);
        $display("Xreg_1 = %h",tms1000_tb.tms1000.ram.Xreg_1[63:0]);
        $display("Xreg_2 = %h",tms1000_tb.tms1000.ram.Xreg_2[63:0]);
        $display("Xreg_3 = %h",tms1000_tb.tms1000.ram.Xreg_3[63:0]);
        $finish;
 -----/\----- EXCLUDED -----/\----- */
   end // initial begin
   always @(r) begin
      case (1'b1)
        r[0] : d0 = q;
        r[1] : d1 = q;
        r[2] : d2 = q;
        r[3] : d3 = q;
        r[4] : d4 = q;
        r[5] : d5 = q;
        r[6] : d6 = q;
        r[7] : d7 = q;
        r[8] : d8 = q;
      endcase
   end
 
   always #5 clk = ~clk;
   always @(posedge clk)
     if (count == 1000) begin
        clk_60 <= ~clk_60;
        count <= 0;
     end else
        count <= count + 1;
endmodule // tms1000_tb