Subversion Repositories tsv

module mkExample (Empty);
    //Reg#(Bit#(8)) r <- mkReg(?);    // don't-care is used for the
    //Reg#(Bit#(8)) r1<- mkReg(8'h33);
    Reg#(Bit#(8)) r2<- mkReg(~0);
    rule every( True );             // reset value of the Reg
        $display("value is %h", r); // the value of r is displayed
    endrule
endmodule