Subversion Repositories tsv

module mkExample (Empty);
    //Reg#(Bit#(8)) r <- mkReg(?);    // don't-care is used for the
    //Reg#(Bit#(8)) r1<- mkReg(8'h33);
    //Reg#(Bit#(8)) r2<- mkReg(~0);
    rule every0(True );             // reset value of the Reg
        $display("value is %h", 0); // the value of r is displayed
        $display("value is %h", x); // the value of r is displayed
    endrule
    rule every1(True );             // reset value of the Reg
        $display("value is %h", 1, 2, x); // the value of r is displayed
    endrule
endmodule

module [M1] mkExample1 (Empty);
    rule every2;             // reset value of the Reg
        $display("OK?");
    endrule
endmodule