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https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
Subversion Repositories turbo8051
[/] [turbo8051/] [trunk/] [fpga/] [altera/] [summary/] [turbo8051.tan.summary] - Rev 34
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--------------------------------------------------------------------------------------Timing Analyzer Summary--------------------------------------------------------------------------------------Type : Worst-case tsuSlack : N/ARequired Time : NoneActual Time : 26.898 nsFrom : wb_xrom_ackTo : oc8051_top:u_8051_core|oc8051_ram_top:oc8051_ram_top1|oc8051_ram_256x8_two_bist:oc8051_idata|rd_data[4]From Clock : --To Clock : xtal_clkFailed Paths : 0Type : Worst-case tcoSlack : N/ARequired Time : NoneActual Time : 19.423 nsFrom : oc8051_top:u_8051_core|oc8051_sfr:oc8051_sfr1|wait_dataTo : wb_xram_adr[14]From Clock : xtal_clkTo Clock : --Failed Paths : 0Type : Worst-case tpdSlack : N/ARequired Time : NoneActual Time : 16.411 nsFrom : wb_xram_rdata[5]To : ext_reg_rdata[13]From Clock : --To Clock : --Failed Paths : 0Type : Worst-case thSlack : N/ARequired Time : NoneActual Time : -0.037 nsFrom : ext_reg_tid[1]To : wb_crossbar:u_wb_crossbar|master_mx_id[2][1]From Clock : --To Clock : xtal_clkFailed Paths : 0Type : Worst-case Minimum Pulse Width Requirement (Low)Slack : -0.564 nsRequired Time : 2.564 nsActual Time : 2.000 nsFrom : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0To : uart_core:u_uart_core|async_fifo:u_txfifo|altsyncram:mem_rtl_0|altsyncram_m8g1:auto_generated|ram_block1a0~porta_we_regFrom Clock : --To Clock : --Failed Paths : 58Type : Worst-case Minimum Pulse Width Requirement (High)Slack : -0.564 nsRequired Time : 2.564 nsActual Time : 2.000 nsFrom : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0To : uart_core:u_uart_core|async_fifo:u_txfifo|altsyncram:mem_rtl_0|altsyncram_m8g1:auto_generated|ram_block1a0~porta_we_regFrom Clock : --To Clock : --Failed Paths : 58Type : Clock Setup: 'clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0'Slack : -21.494 nsRequired Time : 250.00 MHz ( period = 4.000 ns )Actual Time : 39.22 MHz ( period = 25.494 ns )From : oc8051_top:u_8051_core|oc8051_decoder:oc8051_decoder1|altsyncram:WideOr30_rtl_2|altsyncram_ia01:auto_generated|ram_block1a0~porta_address_reg7To : oc8051_top:u_8051_core|oc8051_ram_top:oc8051_ram_top1|oc8051_ram_256x8_two_bist:oc8051_idata|rd_data[4]From Clock : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0To Clock : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0Failed Paths : 310109Type : Clock Setup: 'xtal_clk'Slack : 36.125 nsRequired Time : 25.00 MHz ( period = 40.000 ns )Actual Time : 258.06 MHz ( period = 3.875 ns )From : clkgen:u_clkgen|pll_count[0]To : clkgen:u_clkgen|pll_count[11]From Clock : xtal_clkTo Clock : xtal_clkFailed Paths : 0Type : Clock Hold: 'clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0'Slack : 0.460 nsRequired Time : 250.00 MHz ( period = 4.000 ns )Actual Time : N/AFrom : spi_core:u_spi_core|spi_ctl:u_spi_ctrl|cs_int_nTo : spi_core:u_spi_core|spi_ctl:u_spi_ctrl|cs_int_nFrom Clock : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0To Clock : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0Failed Paths : 0Type : Clock Hold: 'xtal_clk'Slack : 0.460 nsRequired Time : 25.00 MHz ( period = 40.000 ns )Actual Time : N/AFrom : clkgen:u_clkgen|pll_count[6]To : clkgen:u_clkgen|pll_count[6]From Clock : xtal_clkTo Clock : xtal_clkFailed Paths : 0Type : Other violations (see messages)Slack :Required Time :Actual Time :From :To :From Clock :To Clock :Failed Paths : 1Type : Total number of failed pathsSlack :Required Time :Actual Time :From :To :From Clock :To Clock :Failed Paths : 310226--------------------------------------------------------------------------------------
