URL
https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
Subversion Repositories turbo8051
[/] [turbo8051/] [trunk/] [fpga/] [altera/] [summary/] [turbo8051.tan.summary] - Rev 37
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Timing Analyzer Summary
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Type : Worst-case tsu
Slack : N/A
Required Time : None
Actual Time : 26.898 ns
From : wb_xrom_ack
To : oc8051_top:u_8051_core|oc8051_ram_top:oc8051_ram_top1|oc8051_ram_256x8_two_bist:oc8051_idata|rd_data[4]
From Clock : --
To Clock : xtal_clk
Failed Paths : 0
Type : Worst-case tco
Slack : N/A
Required Time : None
Actual Time : 19.423 ns
From : oc8051_top:u_8051_core|oc8051_sfr:oc8051_sfr1|wait_data
To : wb_xram_adr[14]
From Clock : xtal_clk
To Clock : --
Failed Paths : 0
Type : Worst-case tpd
Slack : N/A
Required Time : None
Actual Time : 16.411 ns
From : wb_xram_rdata[5]
To : ext_reg_rdata[13]
From Clock : --
To Clock : --
Failed Paths : 0
Type : Worst-case th
Slack : N/A
Required Time : None
Actual Time : -0.037 ns
From : ext_reg_tid[1]
To : wb_crossbar:u_wb_crossbar|master_mx_id[2][1]
From Clock : --
To Clock : xtal_clk
Failed Paths : 0
Type : Worst-case Minimum Pulse Width Requirement (Low)
Slack : -0.564 ns
Required Time : 2.564 ns
Actual Time : 2.000 ns
From : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0
To : uart_core:u_uart_core|async_fifo:u_txfifo|altsyncram:mem_rtl_0|altsyncram_m8g1:auto_generated|ram_block1a0~porta_we_reg
From Clock : --
To Clock : --
Failed Paths : 58
Type : Worst-case Minimum Pulse Width Requirement (High)
Slack : -0.564 ns
Required Time : 2.564 ns
Actual Time : 2.000 ns
From : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0
To : uart_core:u_uart_core|async_fifo:u_txfifo|altsyncram:mem_rtl_0|altsyncram_m8g1:auto_generated|ram_block1a0~porta_we_reg
From Clock : --
To Clock : --
Failed Paths : 58
Type : Clock Setup: 'clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0'
Slack : -21.494 ns
Required Time : 250.00 MHz ( period = 4.000 ns )
Actual Time : 39.22 MHz ( period = 25.494 ns )
From : oc8051_top:u_8051_core|oc8051_decoder:oc8051_decoder1|altsyncram:WideOr30_rtl_2|altsyncram_ia01:auto_generated|ram_block1a0~porta_address_reg7
To : oc8051_top:u_8051_core|oc8051_ram_top:oc8051_ram_top1|oc8051_ram_256x8_two_bist:oc8051_idata|rd_data[4]
From Clock : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0
To Clock : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0
Failed Paths : 310109
Type : Clock Setup: 'xtal_clk'
Slack : 36.125 ns
Required Time : 25.00 MHz ( period = 40.000 ns )
Actual Time : 258.06 MHz ( period = 3.875 ns )
From : clkgen:u_clkgen|pll_count[0]
To : clkgen:u_clkgen|pll_count[11]
From Clock : xtal_clk
To Clock : xtal_clk
Failed Paths : 0
Type : Clock Hold: 'clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0'
Slack : 0.460 ns
Required Time : 250.00 MHz ( period = 4.000 ns )
Actual Time : N/A
From : spi_core:u_spi_core|spi_ctl:u_spi_ctrl|cs_int_n
To : spi_core:u_spi_core|spi_ctl:u_spi_ctrl|cs_int_n
From Clock : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0
To Clock : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0
Failed Paths : 0
Type : Clock Hold: 'xtal_clk'
Slack : 0.460 ns
Required Time : 25.00 MHz ( period = 40.000 ns )
Actual Time : N/A
From : clkgen:u_clkgen|pll_count[6]
To : clkgen:u_clkgen|pll_count[6]
From Clock : xtal_clk
To Clock : xtal_clk
Failed Paths : 0
Type : Other violations (see messages)
Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 1
Type : Total number of failed paths
Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 310226
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