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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_acc.v] - Rev 53
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////////////////////////////////////////////////////////////////////// //// //// //// 8051 cores acccumulator //// //// //// //// This file is part of the 8051 cores project //// //// http://www.opencores.org/cores/8051/ //// //// //// //// Description //// //// accumulaor register for 8051 core //// //// //// //// To Do: //// //// Nothing //// //// //// //// Author(s): //// //// - Simon Teran, simont@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.13 2003/06/03 17:16:16 simont // `ifdef added. // // Revision 1.12 2003/04/09 16:24:03 simont // change wr_sft to 2 bit wire. // // Revision 1.11 2003/04/09 15:49:42 simont // Register oc8051_sfr dato output, add signal wait_data. // // Revision 1.10 2003/04/07 14:58:02 simont // change sfr's interface. // // Revision 1.9 2003/01/13 14:14:40 simont // replace some modules // // Revision 1.8 2002/11/05 17:23:54 simont // add module oc8051_sfr, 256 bytes internal ram // // Revision 1.7 2002/09/30 17:33:59 simont // prepared header // // // synopsys translate_off `include "oc8051_timescale.v" // synopsys translate_on `include "oc8051_defines.v" module oc8051_acc (clk, rst, bit_in, data_in, data2_in, data_out, wr, wr_bit, wr_addr, p, wr_sfr); input clk, rst, wr, wr_bit, bit_in; input [1:0] wr_sfr; input [7:0] wr_addr, data_in, data2_in; output p; output [7:0] data_out; reg [7:0] data_out; reg [7:0] acc; wire wr_acc, wr2_acc, wr_bit_acc; // //calculates parity assign p = ^acc; assign wr_acc = (wr_sfr==`OC8051_WRS_ACC1) | (wr & !wr_bit & (wr_addr==`OC8051_SFR_ACC)); assign wr2_acc = (wr_sfr==`OC8051_WRS_ACC2); assign wr_bit_acc = (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_ACC)); // //writing to acc always @(wr_sfr or data2_in or wr2_acc or wr_acc or wr_bit_acc or wr_addr[2:0] or data_in or bit_in or data_out) begin if (wr2_acc) acc = data2_in; else if (wr_acc) acc = data_in; else if (wr_bit_acc) case (wr_addr[2:0]) /* synopsys full_case parallel_case */ 3'b000: acc = {data_out[7:1], bit_in}; 3'b001: acc = {data_out[7:2], bit_in, data_out[0]}; 3'b010: acc = {data_out[7:3], bit_in, data_out[1:0]}; 3'b011: acc = {data_out[7:4], bit_in, data_out[2:0]}; 3'b100: acc = {data_out[7:5], bit_in, data_out[3:0]}; 3'b101: acc = {data_out[7:6], bit_in, data_out[4:0]}; 3'b110: acc = {data_out[7], bit_in, data_out[5:0]}; 3'b111: acc = {bit_in, data_out[6:0]}; endcase else acc = data_out; end always @(posedge clk or posedge rst) begin if (rst) data_out <= #1 `OC8051_RST_ACC; else data_out <= #1 acc; end `ifdef OC8051_SIMULATION always @(data_out) if (data_out===8'hxx) begin $display("time ",$time, " faulire: invalid write to ACC (oc8051_acc)"); #22 $finish; end `endif endmodule
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