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[/] [turbocodes/] [trunk/] [src/] [myhdl/] [synthesis.py] - Rev 7
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from myhdl import toVHDL, Signal from misc import delayer clk = Signal(bool(0)) rst = Signal(bool(0)) d = Signal(bool(0)) q = Signal(bool(0)) synthesis_i0 = toVHDL(delayer, clk, rst, d, q)