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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
<table summary="layout" width="66%" border="0" cellpadding="0" cellspacing="0"><tr><td><table summary="layout" width="100%" border="0" cellpadding="2" cellspacing="1">
<tr><td class="header">$Revision: 1.2 $</td><td class="header">G. Hutchison</td></tr>
<tr><td class="header"> </td><td class="header">OpenCores.org</td></tr>
<tr><td class="header"> </td><td class="header">October 2004</td></tr>
</table></td></tr></table>
<div align="right"><span class="title"><br />tv80 Core Documentation</span></div>
<h3>Abstract</h3>
<p>
A synthesizable 8-bit microprocessor which is instruction-set compatable
with the Z80, targetted at embedded and system-on-a-chip designs.
</p><a name="toc"></a><br /><hr />
<h3>Table of Contents</h3>
<p class="toc">
<a href="#anchor1">1.</a>
Background<br />
<a href="#anchor2">2.</a>
Verification Environment<br />
<a href="#anchor3">2.1</a>
Memory Map<br />
<a href="#anchor4">2.2</a>
Control Registers<br />
<a href="#anchor5">2.2.1</a>
Simulation control (0x80)<br />
<a href="#anchor6">2.2.2</a>
Message output (0x81)<br />
<a href="#anchor7">2.2.3</a>
Timeout control (0x82)<br />
<a href="#anchor8">2.2.4</a>
Max timeout (0x84, 0x83)<br />
<a href="#anchor9">2.2.5</a>
Interrupt countdown (0x90)<br />
<a href="#anchor10">2.2.6</a>
Checksum value (0x91)<br />
<a href="#anchor11">2.2.7</a>
Checksum accumulate (0x92)<br />
<a href="#anchor12">2.2.8</a>
Increment on read (0x93)<br />
<a href="#anchor13">2.3</a>
Tool Chain<br />
<a href="#anchor14">2.4</a>
Tests<br />
<a href="#tvs80">2.4.1</a>
tvs80 test<br />
<a href="#rfc.references1">3.</a>
References<br />
<a href="#rfc.authors">§</a>
Author's Address<br />
</p>
<br clear="all" />
<a name="anchor1"></a><br /><hr />
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
<a name="rfc.section.1"></a><h3>1. Background</h3>
<p>The tv80 core was created as a Verilog port of the <a class="info" href="#t80">VHDL T80 core<span>Wallner, D., VHDL T80 Core, .</span></a>[1], for use as a maintenence processor inside an ASIC.
The tv80 has been modified since then for better synthesis
timing/area results, and to incorporate several bug-fixes.
</p>
<p>The T80, and the tv80 derived from it, attempt to maintain the
original cycle timings of the Z80, but have radically different
internal designs and timings. With its target being ASIC and
embedded applications, the tv80 does not attempt to maintain
the original pinout of the Z80.
</p>
<a name="anchor2"></a><br /><hr />
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
<a name="rfc.section.2"></a><h3>2. Verification Environment</h3>
<a name="rfc.section.2.1"></a><h4><a name="anchor3">2.1</a> Memory Map</h4>
<p>
Environment memory space is divided into a 32k ROM region and a 32k RAM
region, as follows:
</p>
<pre>
0000-7FFF: ROM
8000-FFFF: RAM
</pre>
<p>
<p>Environment I/O space is allocated as follows:
</p><pre>
00-0F: Unused
10-1F: Test devices
20-7F: Unused
80-9F: Environment control
A0-FF: Unused
</pre>
<a name="rfc.section.2.2"></a><h4><a name="anchor4">2.2</a> Control Registers</h4>
<a name="rfc.section.2.2.1"></a><h4><a name="anchor5">2.2.1</a> Simulation control (0x80)</h4>
<ul class="text">
<li> Write '01' to end simulation with test passed
</li>
<li> Write '02' to end with test failed
</li>
<li> Write '03' to turn on dumping
</li>
<li> Write '04' to turn off dumping
</li>
</ul>
<a name="rfc.section.2.2.2"></a><h4><a name="anchor6">2.2.2</a> Message output (0x81)</h4>
<p>
Write characters to this port one at a time. When the
newline ('\n', ASCII 0x0A) character is written, the
environment will print out the collected string.
</p>
<a name="rfc.section.2.2.3"></a><h4><a name="anchor7">2.2.3</a> Timeout control (0x82)</h4>
<p>
Bit[0] enables the timeout counter,
Bit[1] resets the counter to 0.
Timeout counter defaults to enabled at simulation start.
</p>
<a name="rfc.section.2.2.4"></a><h4><a name="anchor8">2.2.4</a> Max timeout (0x84, 0x83)</h4>
<p>
Holds 16-bit timeout value (amount of time in clocks before
timeout error occurs).
</p>
<a name="rfc.section.2.2.5"></a><h4><a name="anchor9">2.2.5</a> Interrupt countdown (0x90)</h4>
<p>
When set, starts a countdown (in clocks) until assertion of
the INT_N signal.
</p>
<a name="rfc.section.2.2.6"></a><h4><a name="anchor10">2.2.6</a> Checksum value (0x91)</h4>
<p>This register holds the checksum value of all data
written to the accumulate register. The checksum is a simple
twos-complement checksum, so it can be compared with a CPU-generated
checksum.
</p>
<p>This register is readable and writeable. Writing the register sets
the current checksum value.
</p>
<a name="rfc.section.2.2.7"></a><h4><a name="anchor11">2.2.7</a> Checksum accumulate (0x92)</h4>
<p>This write-only register adds the written value to the value
contained in the Checksum Value register.
</p>
<a name="rfc.section.2.2.8"></a><h4><a name="anchor12">2.2.8</a> Increment on read (0x93)</h4>
<p>This register increments every time it is read, so reading it
repeatedly generates an incrementing sequence. It can be reset
by writing it to a new starting value.
</p>
<a name="rfc.section.2.3"></a><h4><a name="anchor13">2.3</a> Tool Chain</h4>
<p>The minimum toolchain required to simulate the tv80 is the
<a class="info" href="#cver">CVer<span>Vanvick, A., GPL Cver Simulator, .</span></a>[3] Verilog simulator, and the
<a class="info" href="#sdcc">SDCC<span>, Small Device C Compiler, .</span></a>[2] compiler/assembler/linker. In
addition, to run the <a class="info" href="#tvs80">tvs80<span>tvs80 test</span></a> instruction
test suite, the <a class="info" href="#dosbox">DOSBox<span>, DOSBox, .</span></a>[4] DOS emulator
is required.
</p>
<a name="rfc.section.2.4"></a><h4><a name="anchor14">2.4</a> Tests</h4>
<p>Most of the tests in the tv80 environment are written in C, and should
be compiled with the <a class="info" href="#sdcc">sdcc<span>, Small Device C Compiler, .</span></a>[2] compiler.
</p>
<a name="rfc.section.2.4.1"></a><h4><a name="tvs80">2.4.1</a> tvs80 test</h4>
<p>The tvs80 test is different than the rest of the tests, and is
written in its own flavor of assembly language. This test provides
a fairly comprehensive Z80 instruction test.
</p>
<p>The assembler for this test only runs under DOS. To assemble
under Unix/Linux, the <a class="info" href="#dosbox">"dosbox" DOS emulator<span>, DOSBox, .</span></a>[4] is required. A script
to run the assembler under dosbox, as well as the tvs80.asm source,
is checked in under the "tests/tvs80" directory.
</p>
<a name="rfc.references1"></a><br /><hr />
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
<h3>3 References</h3>
<table width="99%" border="0">
<tr><td class="author-text" valign="top"><a name="t80">[1]</a></td>
<td class="author-text">Wallner, D., "<a href="http://www.opencores.org/projects.cgi/web/t80/overview">VHDL T80 Core</a>".</td></tr>
<tr><td class="author-text" valign="top"><a name="sdcc">[2]</a></td>
<td class="author-text">"<a href="http://sdcc.sourceforge.net">Small Device C Compiler</a>".</td></tr>
<tr><td class="author-text" valign="top"><a name="cver">[3]</a></td>
<td class="author-text">Vanvick, A., "<a href="http://www.pragmatic-c.com/gpl-cver">GPL Cver Simulator</a>".</td></tr>
<tr><td class="author-text" valign="top"><a name="dosbox">[4]</a></td>
<td class="author-text">"<a href="http://dosbox.sourceforge.net">DOSBox</a>".</td></tr>
</table>
<a name="rfc.authors"></a><br /><hr />
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
<h3>Author's Address</h3>
<table width="99%" border="0" cellpadding="0" cellspacing="0">
<tr><td class="author-text"> </td>
<td class="author-text">Guy Hutchison</td></tr>
<tr><td class="author-text"> </td>
<td class="author-text">OpenCores.org</td></tr>
<tr><td class="author" align="right">EMail: </td>
<td class="author-text"><a href="mailto:ghutchis@opencores.org">ghutchis@opencores.org</a></td></tr>
</table>
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