Subversion Repositories uart16750

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The top-word is always available at the output (no read-request/delay).Rules for FIFO generation with vendor tools:can be used for a Altera Cyclone II.In slib_fifo.vhd is a generic FIFO (for simulation), slib_fifo_cyclone2.vhdThe FIFO implementation should be replaced for the specific device.uart_interrupt.vhd:     Interrupt register and generationuart_baudgen.vhd:       Baudrate generatoruart_transmitter.vhd:   UART transmitter partuart_receiver.vhd:      UART receiver partuart_16750.vhd:         Top level fileFiles:- *DOS- *BSD- Windows 2000/XP/Vista- Linux 2.2/2.4/2.6standard hardware and than tested with standard OS drivers from:The core was synthesized on a Altera Cyclone II, connected to x86can be used for simulation or real-hardware testing.A script is used to create a extensive functional stimuli file whichTests:- Variable character time-out counter- Automatic flow controlTodo:- All interrupts sources/modes- Control lines RTS/CTS/DTR/DSR/DCD/RI/OUT1/OUT2- Receiver FIFO trigger levels 1/4/8/14/16/32/56- 16/64 byte FIFO mode- Supports 1/1.5/2 stop bit generation- None/Even/Odd parity bit generation and detection- Supports 5/6/7/8 bit characters- Baudrate generator with clock enable- Register compatible to 16550/16750- Pin compatible to 16550/16750- Full synchronous designFeatures:Implements a synthesizable 16550/16750 UART core.Description:==========================================UART16750 1.0 (C) 2008-2009 Sebastian Witt==========================================