URL
https://opencores.org/ocsvn/uart16750/uart16750/trunk
Subversion Repositories uart16750
[/] [uart16750/] [tags/] [Import/] [sim/] [rtl_sim/] [src/] [uart_stim.dat] - Rev 3
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#WAIT 10#SET 0 1 1 1 1#LOG UART: Initializing...#WR 001 00000000#WR 010 00000000#WR 011 00000000#WR 100 00000000#WR 111 00000000#LOG UART: Checking registers after reset...#RD 000 00000000#RD 000 00000000#RD 001 00000000#RD 010 00000001#RD 011 00000000#RD 100 00000000#RD 101 01100000#RD 110 00001111#RD 111 00000000#LOG UART: Enabling local LOOP mode...#WR 100 00010000#RD 100 00010000#LOG UART: Setting baudrate to 115200#WR 011 10000000#WR 000 00000001#WR 001 00000000#RD 011 10000000#RD 000 00000001#RD 001 00000000#WR 011 00000000#RD 011 00000000#LOG UART: Enabling interrupts...#WR 001 00001111#RD 001 00001111#RD 010 00000010#RD 010 00000001#LOG UART: Checking control lines...#WR 100 00010001#RD 100 00010001#RD 010 00000000#RD 110 00100010#RD 110 00100000#RD 010 00000001#WR 100 00010011#RD 100 00010011#RD 010 00000000#RD 110 00110001#RD 110 00110000#RD 010 00000001#WR 100 00010111#RD 100 00010111#WR 100 00010011#RD 100 00010011#RD 010 00000000#RD 110 00110100#RD 010 00000001#RD 110 00110000#WR 100 00011011#RD 100 00011011#RD 010 00000000#RD 110 10111000#RD 110 10110000#RD 010 00000001#WR 100 00010000#RD 100 00010000#RD 010 00000000#RD 110 00001011#RD 010 00000001#LOG UART: Checking interrupt priority control...#WR 100 00010001#WR 100 00010000#WR 000 00010010#WAIT 2604#WR 011 01000000#WAIT 2604#WR 011 00000000#RD 010 00000110#RD 101 01111011#RD 010 00000100#RD 010 00000100#RD 000 00000000#WR 000 00110100#WAIT 2604#RD 101 01100001#WR 000 01010110#RD 010 00000100#WAIT 2604#RD 010 00000110#RD 101 01100011#RD 101 01100001#RD 010 00000100#RD 000 00010110#RD 010 00000010#RD 010 00000000#RD 010 00000000#RD 110 00000010#RD 010 00000001#WR 000 01111000#WAIT 2604#RD 010 00000100#RD 000 00011000#RD 010 00000010#RD 010 00000001#LOG UART: Setting LCR to 0x00#WR 011 00000000#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2604#WR 000 01010101#WAIT 2604#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2604#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2604#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01000000#RD 011 01000000#WAIT 5208#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00000000#RD 011 00000000#WAIT 5208#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x01#WR 011 00000001#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01000001#RD 011 01000001#WAIT 5787#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00000001#RD 011 00000001#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x02#WR 011 00000010#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01000010#RD 011 01000010#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00000010#RD 011 00000010#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x03#WR 011 00000011#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01000011#RD 011 01000011#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00000011#RD 011 00000011#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x04#WR 011 00000100#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01000100#RD 011 01000100#WAIT 5787#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00000100#RD 011 00000100#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x05#WR 011 00000101#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01000101#RD 011 01000101#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00000101#RD 011 00000101#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x06#WR 011 00000110#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01000110#RD 011 01000110#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00000110#RD 011 00000110#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x07#WR 011 00000111#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3761#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3761#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01000111#RD 011 01000111#WAIT 7523#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00000111#RD 011 00000111#WAIT 7523#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x08#WR 011 00001000#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01001000#RD 011 01001000#WAIT 5787#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00001000#RD 011 00001000#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x09#WR 011 00001001#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01001001#RD 011 01001001#WAIT 6365#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00001001#RD 011 00001001#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x0A#WR 011 00001010#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01001010#RD 011 01001010#WAIT 6944#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00001010#RD 011 00001010#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x0B#WR 011 00001011#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3761#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3761#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01001011#RD 011 01001011#WAIT 7523#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00001011#RD 011 00001011#WAIT 7523#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x0C#WR 011 00001100#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01001100#RD 011 01001100#WAIT 6365#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00001100#RD 011 00001100#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x0D#WR 011 00001101#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01001101#RD 011 01001101#WAIT 6944#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00001101#RD 011 00001101#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x0E#WR 011 00001110#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3761#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3761#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01001110#RD 011 01001110#WAIT 7523#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00001110#RD 011 00001110#WAIT 7523#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x0F#WR 011 00001111#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 4050#WR 000 01010101#WAIT 4050#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 4050#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 4050#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01001111#RD 011 01001111#WAIT 8101#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00001111#RD 011 00001111#WAIT 8101#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x10#WR 011 00010000#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2604#WR 000 01010101#WAIT 2604#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2604#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2604#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010000#RD 011 01010000#WAIT 5208#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00010000#RD 011 00010000#WAIT 5208#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x11#WR 011 00010001#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010001#RD 011 01010001#WAIT 5787#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00010001#RD 011 00010001#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x12#WR 011 00010010#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010010#RD 011 01010010#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00010010#RD 011 00010010#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x13#WR 011 00010011#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010011#RD 011 01010011#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00010011#RD 011 00010011#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x14#WR 011 00010100#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010100#RD 011 01010100#WAIT 5787#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00010100#RD 011 00010100#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x15#WR 011 00010101#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010101#RD 011 01010101#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00010101#RD 011 00010101#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x16#WR 011 00010110#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010110#RD 011 01010110#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00010110#RD 011 00010110#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x17#WR 011 00010111#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3761#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3761#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010111#RD 011 01010111#WAIT 7523#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00010111#RD 011 00010111#WAIT 7523#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x18#WR 011 00011000#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01011000#RD 011 01011000#WAIT 5787#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00011000#RD 011 00011000#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x19#WR 011 00011001#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01011001#RD 011 01011001#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00011001#RD 011 00011001#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x1A#WR 011 00011010#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01011010#RD 011 01011010#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00011010#RD 011 00011010#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x1B#WR 011 00011011#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3761#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3761#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01011011#RD 011 01011011#WAIT 7523#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00011011#RD 011 00011011#WAIT 7523#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x1C#WR 011 00011100#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01011100#RD 011 01011100#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00011100#RD 011 00011100#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x1D#WR 011 00011101#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01011101#RD 011 01011101#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00011101#RD 011 00011101#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x1E#WR 011 00011110#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3761#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3761#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01011110#RD 011 01011110#WAIT 7523#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00011110#RD 011 00011110#WAIT 7523#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x1F#WR 011 00011111#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 4050#WR 000 01010101#WAIT 4050#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 4050#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 4050#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01011111#RD 011 01011111#WAIT 8101#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00011111#RD 011 00011111#WAIT 8101#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x20#WR 011 00100000#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2604#WR 000 01010101#WAIT 2604#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2604#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2604#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01100000#RD 011 01100000#WAIT 5208#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00100000#RD 011 00100000#WAIT 5208#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x21#WR 011 00100001#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01100001#RD 011 01100001#WAIT 5787#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00100001#RD 011 00100001#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x22#WR 011 00100010#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01100010#RD 011 01100010#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00100010#RD 011 00100010#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x23#WR 011 00100011#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01100011#RD 011 01100011#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00100011#RD 011 00100011#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x24#WR 011 00100100#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01100100#RD 011 01100100#WAIT 5787#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00100100#RD 011 00100100#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x25#WR 011 00100101#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01100101#RD 011 01100101#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00100101#RD 011 00100101#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x26#WR 011 00100110#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01100110#RD 011 01100110#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00100110#RD 011 00100110#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x27#WR 011 00100111#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3761#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3761#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01100111#RD 011 01100111#WAIT 7523#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00100111#RD 011 00100111#WAIT 7523#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x28#WR 011 00101000#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01101000#RD 011 01101000#WAIT 5787#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00101000#RD 011 00101000#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x29#WR 011 00101001#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01101001#RD 011 01101001#WAIT 6365#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00101001#RD 011 00101001#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x2A#WR 011 00101010#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01101010#RD 011 01101010#WAIT 6944#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00101010#RD 011 00101010#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x2B#WR 011 00101011#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3761#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3761#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01101011#RD 011 01101011#WAIT 7523#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00101011#RD 011 00101011#WAIT 7523#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x2C#WR 011 00101100#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01101100#RD 011 01101100#WAIT 6365#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00101100#RD 011 00101100#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x2D#WR 011 00101101#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01101101#RD 011 01101101#WAIT 6944#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00101101#RD 011 00101101#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x2E#WR 011 00101110#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3761#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3761#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01101110#RD 011 01101110#WAIT 7523#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00101110#RD 011 00101110#WAIT 7523#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x2F#WR 011 00101111#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 4050#WR 000 01010101#WAIT 4050#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 4050#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 4050#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01101111#RD 011 01101111#WAIT 8101#RD 010 00000110#RD 101 01111101#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00101111#RD 011 00101111#WAIT 8101#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x30#WR 011 00110000#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2604#WR 000 01010101#WAIT 2604#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2604#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2604#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2604#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01110000#RD 011 01110000#WAIT 5208#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00110000#RD 011 00110000#WAIT 5208#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x31#WR 011 00110001#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01110001#RD 011 01110001#WAIT 5787#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00110001#RD 011 00110001#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x32#WR 011 00110010#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01110010#RD 011 01110010#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00110010#RD 011 00110010#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x33#WR 011 00110011#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01110011#RD 011 01110011#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00110011#RD 011 00110011#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x34#WR 011 00110100#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01110100#RD 011 01110100#WAIT 5787#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00110100#RD 011 00110100#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x35#WR 011 00110101#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01110101#RD 011 01110101#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00110101#RD 011 00110101#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x36#WR 011 00110110#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01110110#RD 011 01110110#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00110110#RD 011 00110110#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x37#WR 011 00110111#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3761#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3761#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01110111#RD 011 01110111#WAIT 7523#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00110111#RD 011 00110111#WAIT 7523#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x38#WR 011 00111000#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01111000#RD 011 01111000#WAIT 5787#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00111000#RD 011 00111000#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x39#WR 011 00111001#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01111001#RD 011 01111001#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00111001#RD 011 00111001#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x3A#WR 011 00111010#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01111010#RD 011 01111010#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00111010#RD 011 00111010#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x3B#WR 011 00111011#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3761#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3761#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01111011#RD 011 01111011#WAIT 7523#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00111011#RD 011 00111011#WAIT 7523#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x3C#WR 011 00111100#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01111100#RD 011 01111100#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00111100#RD 011 00111100#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x3D#WR 011 00111101#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01111101#RD 011 01111101#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00111101#RD 011 00111101#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x3E#WR 011 00111110#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3761#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3761#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3761#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3761#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01111110#RD 011 01111110#WAIT 7523#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00111110#RD 011 00111110#WAIT 7523#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x3F#WR 011 00111111#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 4050#WR 000 01010101#WAIT 4050#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 4050#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 4050#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 4050#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01111111#RD 011 01111111#WAIT 8101#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00111111#RD 011 00111111#WAIT 8101#RD 101 01100000#RD 010 00000001#WR 011 00000000#LOG UART: Enabling FIFO...#WR 010 00000001#RD 010 11000010#RD 010 11000001#LOG UART: Testing FIFO trigger level 1 byte...#WR 010 00000001#WR 000 00000000#WAIT 10416#RD 010 11001100#RD 101 01100001#RD 000 00000000#RD 010 11000010#RD 101 01100000#RD 010 11000001#LOG UART: Testing FIFO trigger level 4 byte...#WR 010 01000001#WR 000 00000000#WR 000 00000001#WR 000 00000010#WAIT 18229#RD 010 11001100#RD 101 01100001#RD 000 00000000#WR 000 00000000#WR 000 00000001#WAIT 15625#RD 010 11001100#WAIT 5208#RD 101 01100001#RD 000 00000001#RD 010 11000010#RD 101 01100001#RD 010 11000001#RD 000 00000010#RD 000 00000000#RD 000 00000001#RD 101 01100000#RD 010 11000001#LOG UART: Testing FIFO trigger level 8 byte...#WR 010 10000001#WR 000 00000000#WR 000 00000001#WR 000 00000010#WR 000 00000011#WR 000 00000100#WR 000 00000101#WR 000 00000110#RD 010 11000001#WAIT 28645#RD 010 11001100#RD 101 01100001#RD 000 00000000#RD 010 11000010#RD 010 11000001#WR 000 00000000#WR 000 00000001#WAIT 15625#RD 010 11001100#WAIT 5208#RD 101 01100001#RD 000 00000001#RD 010 11000010#RD 101 01100001#RD 010 11000001#RD 000 00000010#RD 101 01100001#RD 000 00000011#RD 101 01100001#RD 000 00000100#RD 101 01100001#RD 000 00000101#RD 101 01100001#RD 000 00000110#RD 101 01100001#RD 000 00000000#RD 101 01100001#RD 000 00000001#RD 101 01100000#RD 010 11000001#LOG UART: Testing FIFO trigger level 14 byte...#WR 010 11000001#WR 000 00000000#WR 000 00000001#WR 000 00000010#WR 000 00000011#WR 000 00000100#WR 000 00000101#WR 000 00000110#WR 000 00000111#WR 000 00001000#WR 000 00001001#WR 000 00001010#WR 000 00001011#WR 000 00001100#WAIT 44270#RD 010 11001100#RD 101 01100001#RD 000 00000000#RD 010 11000010#RD 010 11000001#WR 000 00000000#WR 000 00000001#WAIT 15625#RD 010 11001100#RD 101 01100001#RD 000 00000001#RD 010 11000010#RD 101 01100001#RD 010 11000001#RD 000 00000010#RD 101 01100001#RD 000 00000011#RD 101 01100001#RD 000 00000100#RD 101 01100001#RD 000 00000101#RD 101 01100001#RD 000 00000110#RD 101 01100001#RD 000 00000111#RD 101 01100001#RD 000 00001000#RD 101 01100001#RD 000 00001001#RD 101 01100001#RD 000 00001010#RD 101 01100001#RD 000 00001011#RD 101 01100001#RD 000 00001100#RD 101 01100001#RD 000 00000000#RD 101 01100001#RD 000 00000001#RD 101 01100000#RD 010 11000001#LOG UART: Testing FIFO overrun...#WR 010 00000001#WR 000 00000000#WR 000 00000001#WR 000 00000010#WR 000 00000011#WR 000 00000100#WR 000 00000101#WR 000 00000110#WR 000 00000111#WR 000 00001000#WR 000 00001001#WR 000 00001010#WR 000 00001011#WR 000 00001100#WR 000 00001101#WR 000 00001110#WR 000 00001111#WR 000 00010000#WAIT 44270#RD 010 11000110#RD 101 01100011#RD 010 11001100#RD 101 01100001#RD 000 00000000#RD 010 11000100#RD 101 01100001#WR 010 00000011#RD 101 01100000#RD 010 11000010#RD 010 11000001#LOG UART: Miscellaneous FIFO tests...#WR 011 00000011#WR 001 00000001#RD 010 11000001#WR 010 11000001#RD 010 11000001#RD 101 01100000#LOG UART: Sending 8 words#WR 000 00000000#WR 000 00000001#WR 000 00000010#WR 000 00000011#WR 000 00000100#WR 000 00000101#WR 000 00000110#WR 000 00000111#RD 010 11000001#WAIT 41666#RD 010 11001100#RD 101 01100001#LOG UART: Receiving 8 words#RD 000 00000000#RD 000 00000001#RD 000 00000010#RD 000 00000011#RD 000 00000100#RD 000 00000101#RD 000 00000110#RD 000 00000111#RD 010 11000001#RD 101 01100000#LOG UART: Sending 16 words#WR 000 00000000#WR 000 00000001#WR 000 00000010#WR 000 00000011#WR 000 00000100#WR 000 00000101#WR 000 00000110#WR 000 00000111#WR 000 00001000#WR 000 00001001#WR 000 00001010#WR 000 00001011#WR 000 00001100#WR 000 00001101#WR 000 00001110#WR 000 00001111#WAIT 13888#LOG UART: Receiving 4 words#RD 000 00000000#RD 000 00000001#RD 000 00000010#RD 000 00000011#LOG UART: Sending 4 words#WR 000 00000000#WR 000 00000001#WR 000 00000010#WR 000 00000011#WAIT 41666#LOG UART: Receiving 12 words#RD 000 00000100#RD 000 00000101#RD 000 00000110#RD 000 00000111#RD 000 00001000#RD 000 00001001#RD 000 00001010#RD 000 00001011#RD 000 00001100#RD 000 00001101#RD 000 00001110#RD 000 00001111#WAIT 27777#LOG UART: Receiving 2 words#RD 000 00000000#RD 000 00000001#RD 010 11000001#RD 101 01100001#LOG UART: Sending 40 words#WR 000 00000000#WR 000 00000001#WR 000 00000010#WR 000 00000011#WR 000 00000100#WR 000 00000101#WR 000 00000110#WR 000 00000111#WR 000 00001000#WR 000 00001001#WR 000 00001010#WR 000 00001011#WR 000 00001100#WR 000 00001101#WR 000 00001110#WR 000 00001111#WR 000 00010000#WR 000 00010001#WR 000 00010010#WR 000 00010011#WR 000 00010100#WR 000 00010101#WR 000 00010110#WR 000 00010111#WR 000 00011000#WR 000 00011001#WR 000 00011010#WR 000 00011011#WR 000 00011100#WR 000 00011101#WR 000 00011110#WR 000 00011111#WR 000 00100000#WR 000 00100001#WR 000 00100010#WR 000 00100011#WR 000 00100100#WR 000 00100101#WR 000 00100110#WR 000 00100111#WAIT 13888#RD 101 00000001#WAIT 69444#RD 101 01100011#RD 010 11001100#LOG UART: Receiving 3 words#RD 000 00000010#RD 000 00000011#RD 000 00000000#RD 010 11000001#LOG UART: Receiving 13 words#RD 000 00000001#RD 000 00000010#RD 000 00000011#RD 000 00000100#RD 000 00000101#RD 000 00000110#RD 000 00000111#RD 000 00001000#RD 000 00001001#RD 000 00001010#RD 000 00001011#RD 000 00001100#RD 000 00001101#RD 101 01100000#RD 010 11000001#LOG UART: Testing FIFO error counter...#WR 001 00000101#LOG UART: Sending 2 words#WR 000 00000000#WR 000 00000001#WAIT 6944#LOG UART: Sending break#WR 011 01000011#WAIT 3472#WR 011 00000011#RD 101 11100001#LOG UART: Sending 4 words#WR 000 00000000#WR 000 00000001#WR 000 00000010#WR 000 00000011#WAIT 13888#LOG UART: Sending break#WR 011 01000011#WAIT 3472#WR 011 00000011#LOG UART: Sending 2 words#WR 000 00000000#WR 000 00000001#WAIT 20833#RD 101 11100001#RD 010 11001100#LOG UART: Reading 2 words#RD 000 00000000#RD 101 11100001#RD 000 00000001#RD 010 11000110#RD 101 11111001#RD 101 11100001#LOG UART: Reading break word#RD 000 00000000#RD 010 11000001#RD 101 11100001#LOG UART: Reading 4 words#RD 000 00000000#RD 101 11100001#RD 000 00000001#RD 101 11100001#RD 000 00000010#RD 101 11100001#RD 000 00000011#RD 010 11000110#RD 101 11111001#RD 010 11000001#RD 101 11100001#RD 101 11100001#RD 101 11100001#LOG UART: Reading break word#RD 000 00000000#RD 101 01100001#RD 000 00000000#RD 101 01100001#RD 000 00000001#RD 101 01100000#LOG UART: Sending break#WR 011 01000011#WAIT 3472#WR 011 00000011#RD 010 11000110#RD 101 11111001#RD 010 11000001#RD 101 11100001#RD 101 11100001#LOG UART: Reading break word#RD 000 00000000#RD 101 01100000#LOG UART: FIFO test end
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