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Design Assistant report for UART16750Tue Feb 17 23:02:41 2009Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version---------------------; Table of Contents ;---------------------1. Legal Notice2. Design Assistant Summary3. Design Assistant Settings4. Information only Violations5. Design Assistant Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2008 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+-------------------------------------------------------------------------+; Design Assistant Summary ;+-----------------------------------+-------------------------------------+; Design Assistant Status ; Analyzed - Tue Feb 17 23:02:41 2009 ;; Revision Name ; UART16750 ;; Top-level Entity Name ; UART16750 ;; Family ; Cyclone II ;; Total Critical Violations ; 0 ;; Total High Violations ; 0 ;; Total Medium Violations ; 0 ;; Total Information only Violations ; 55 ;+-----------------------------------+-------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Design Assistant Settings ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+; Option ; Setting ; To ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+; Design Assistant mode ; Post-Fitting ; ;; Threshold value for clock net not mapped to clock spines rule ; 25 ; ;; Minimum number of clock port feed by gated clocks ; 30 ; ;; Minimum number of node fan-out ; 30 ; ;; Maximum number of nodes to report ; 50 ; ;; Rule C101: Gated clock should be implemented according to the Altera standard scheme ; On ; ;; Rule C102: Logic cell should not be used to generate inverted clock ; On ; ;; Rule C103: Gated clock is not feeding at least a pre-defined number of clock port to effectively save power ; On ; ;; Rule C104: Clock signal source should drive only input clock ports ; On ; ;; Rule C105: Clock signal should be a global signal (Rule applies during post-fitting analysis. This rule applies during both post-fitting analysis and post-synthesis analysis if the design targets a MAX 3000 or MAX 7000 device. For more information, see the Help for the rule.) ; On ; ;; Rule C106: Clock signal source should not drive registers that are triggered by different clock edges ; On ; ;; Rule R101: Combinational logic used as a reset signal should be synchronized ; On ; ;; Rule R102: External reset should be synchronized using two cascaded registers ; On ; ;; Rule R103: External reset should be correctly synchronized ; On ; ;; Rule R104: The reset signal that is generated in one clock domain and is used in the other clock domain, should be correctly synchronized ; On ; ;; Rule R105: The reset signal that is generated in one clock domain and is used in the other clock domain, should be synchronized ; On ; ;; Rule T101: Nodes with more than the specified number of fan-outs ; On ; ;; Rule T102: Top nodes with the highest number of fan-outs ; On ; ;; Rule A101: Design should not contain combinational loops ; On ; ;; Rule A102: Register output should not drive its own control signal directly or through combinational logic ; On ; ;; Rule A103: Design should not contain delay chains ; On ; ;; Rule A104: Design should not contain ripple clock structures ; On ; ;; Rule A105: Pulses should not be implemented asynchronously ; On ; ;; Rule A106: Multiple pulses should not be generated in design ; On ; ;; Rule A107: Design should not contain SR latches ; On ; ;; Rule A108: Design should not contain latches ; On ; ;; Rule A109: Combinational logic should not directly drive write enable signal of asynchronous RAM ; On ; ;; Rule A110: Design should not contain asynchronous memory ; On ; ;; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source ; On ; ;; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; On ; ;; Rule S103: More than one asynchronous signal port of the same register should not be driven by the same signal source ; On ; ;; Rule S104: Clock port and any other signal port of same register should not be driven by the same signal source ; On ; ;; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains ; On ; ;; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain ; On ; ;; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains ; On ; ;; Rule H101: Only one VREF pin should be assigned to the HardCopy test pin in an I/O bank (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On ; ;; Rule H102: PLL clock output drives multiple clock network types (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On ; ;; Rule M101: Data bits are not synchronized when transferred to the state machine of asynchronous clock domains ; On ; ;; Rule M102: No reset signal defined to initialize the state machine ; On ; ;; Rule M103: State machine should not contain an unreachable state ; On ; ;; Rule M104: State machine should not contain a deadlock state ; On ; ;; Rule M105: State machine should not contain a dead transition ; On ; ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Information only Violations ;+------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+---------+; Rule name ; Name ; Fan-Out ;+------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+---------+; Rule T101: Nodes with more than the specified number of fan-outs ; CLK~clkctrl ; 288 ;; Rule T101: Nodes with more than the specified number of fan-outs ; inst1~clkctrl ; 224 ;; Rule T101: Nodes with more than the specified number of fan-outs ; ~GND ; 34 ;; Rule T101: Nodes with more than the specified number of fan-outs ; uart_16750:inst|iRXFIFOClear ; 41 ;; Rule T101: Nodes with more than the specified number of fan-outs ; uart_16750:inst|iFCR_TXFIFOReset ; 33 ;; Rule T102: Top nodes with the highest number of fan-outs ; CLK~clkctrl ; 288 ;; Rule T102: Top nodes with the highest number of fan-outs ; inst1~clkctrl ; 224 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iRXFIFOClear ; 41 ;; Rule T102: Top nodes with the highest number of fan-outs ; ~GND ; 34 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iFCR_TXFIFOReset ; 33 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff ; 22 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; 17 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_baudgen:UART_BG16|Equal0~179 ; 17 ;; Rule T102: Top nodes with the highest number of fan-outs ; A[1] ; 15 ;; Rule T102: Top nodes with the highest number of fan-outs ; A[0] ; 15 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|Mux0~160 ; 14 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_clock_div:UART_BG2|iQ ; 14 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ ; 14 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iFCR_FIFOEnable ; 13 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iRXFIFORead~50 ; 13 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|iDataCountInit ; 12 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|State~57 ; 12 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCR[7] ; 12 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iA[1] ; 12 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4] ; 12 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|Mux5~105 ; 12 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_wreq ; 12 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iMCR[4] ; 11 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; 11 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[0] ; 11 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_rreq ; 11 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[1] ; 11 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_wreq~186 ; 11 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_rreq ; 10 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCR[1] ; 10 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[2] ; 10 ;; Rule T102: Top nodes with the highest number of fan-outs ; A[2] ; 10 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDIN[0] ; 10 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iA[0] ; 10 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iTXFIFORead ; 10 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDIN[1] ; 9 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCR[0] ; 9 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_transmitter:UART_TX|CState~1612 ; 9 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|RX_DATACOUNT~0 ; 9 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iSCRWrite~35 ; 8 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDIN[2] ; 8 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|Mux5~104 ; 8 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDLLWrite~31 ; 8 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCRWrite~28 ; 8 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDLMWrite~32 ; 8 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; 8 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iRXFIFOWrite ; 8 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDIN[5] ; 7 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iA[2] ; 7 ;; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCR[3] ; 7 ;+------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+---------++---------------------------+; Design Assistant Messages ;+---------------------------+Info: *******************************************************************Info: Running Quartus II Design AssistantInfo: Version 8.0 Build 215 05/29/2008 SJ Full VersionInfo: Processing started: Tue Feb 17 23:02:40 2009Info: Command: quartus_drc --read_settings_files=off --write_settings_files=off UART16750 -c UART16750Info: (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 5 node(s) with highest fan-out.Info: Node "CLK~clkctrl" has 288 fan-out(s)Info: Node "inst1~clkctrl" has 224 fan-out(s)Info: Node "~GND" has 34 fan-out(s)Info: Node "uart_16750:inst|iRXFIFOClear" has 41 fan-out(s)Info: Node "uart_16750:inst|iFCR_TXFIFOReset" has 33 fan-out(s)Info: (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out.Info: Node "CLK~clkctrl" has 288 fan-out(s)Info: Node "inst1~clkctrl" has 224 fan-out(s)Info: Node "uart_16750:inst|iRXFIFOClear" has 41 fan-out(s)Info: Node "~GND" has 34 fan-out(s)Info: Node "uart_16750:inst|iFCR_TXFIFOReset" has 33 fan-out(s)Info: Node "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff" has 22 fan-out(s)Info: Node "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff" has 17 fan-out(s)Info: Node "uart_16750:inst|uart_baudgen:UART_BG16|Equal0~179" has 17 fan-out(s)Info: Node "A[1]" has 15 fan-out(s)Info: Node "A[0]" has 15 fan-out(s)Info: Node "uart_16750:inst|Mux0~160" has 14 fan-out(s)Info: Node "uart_16750:inst|slib_clock_div:UART_BG2|iQ" has 14 fan-out(s)Info: Node "uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ" has 14 fan-out(s)Info: Node "uart_16750:inst|iFCR_FIFOEnable" has 13 fan-out(s)Info: Node "uart_16750:inst|iRXFIFORead~50" has 13 fan-out(s)Info: Node "uart_16750:inst|uart_receiver:UART_RX|iDataCountInit" has 12 fan-out(s)Info: Node "uart_16750:inst|State~57" has 12 fan-out(s)Info: Node "uart_16750:inst|iLCR[7]" has 12 fan-out(s)Info: Node "uart_16750:inst|iA[1]" has 12 fan-out(s)Info: Node "uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4]" has 12 fan-out(s)Info: Node "uart_16750:inst|Mux5~105" has 12 fan-out(s)Info: Node "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_wreq" has 12 fan-out(s)Info: Node "uart_16750:inst|iMCR[4]" has 11 fan-out(s)Info: Node "uart_16750:inst|uart_receiver:UART_RX|CState.idle" has 11 fan-out(s)Info: Node "uart_16750:inst|uart_receiver:UART_RX|iDataCount[0]" has 11 fan-out(s)Info: Node "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_rreq" has 11 fan-out(s)Info: Node "uart_16750:inst|uart_receiver:UART_RX|iDataCount[1]" has 11 fan-out(s)Info: Node "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_wreq~186" has 11 fan-out(s)Info: Node "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_rreq" has 10 fan-out(s)Info: Node "uart_16750:inst|iLCR[1]" has 10 fan-out(s)Info: Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.Info: Design Assistant information: finished post-fitting analysis of current design -- generated 55 information messages and 0 warning messagesInfo: Quartus II Design Assistant was successful. 0 errors, 0 warningsInfo: Peak virtual memory: 115 megabytesInfo: Processing ended: Tue Feb 17 23:02:41 2009Info: Elapsed time: 00:00:01Info: Total CPU time (on all processors): 00:00:01
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