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https://opencores.org/ocsvn/uart16750/uart16750/trunk
Subversion Repositories uart16750
[/] [uart16750/] [trunk/] [syn/] [Altera/] [CycloneII/] [UART16750.fit.smsg] - Rev 17
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Extra Info: Performing register packing on registers with non-logic cell location assignmentsExtra Info: Completed register packing on registers with non-logic cell location assignmentsExtra Info: Started Fast Input/Output/OE register processingExtra Info: Finished Fast Input/Output/OE register processingExtra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and densityExtra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks