URL
https://opencores.org/ocsvn/uart16750/uart16750/trunk
Subversion Repositories uart16750
[/] [uart16750/] [trunk/] [syn/] [Altera/] [CycloneII/] [UART16750.map.rpt] - Rev 17
Compare with Previous | Blame | View Log
Analysis & Synthesis report for UART16750
Tue Feb 17 23:02:31 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis RAM Summary
8. State Machine - |UART16750|uart_16750:inst|\UART_TXPROC:State
9. State Machine - |UART16750|uart_16750:inst|uart_receiver:UART_RX|CState
10. State Machine - |UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState
11. General Register Statistics
12. Inverted Register Statistics
13. Multiplexer Restructuring Statistics (Restructuring Performed)
14. Source assignments for uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram
15. Source assignments for uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram
16. Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_CTS
17. Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_DSR
18. Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_DCD
19. Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_RI
20. Parameter Settings for User Entity Instance: uart_16750:inst|slib_clock_div:UART_BG2
21. Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_TXFF
22. Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component
23. Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_RXFF
24. Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component
25. Parameter Settings for User Entity Instance: uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC
26. Parameter Settings for User Entity Instance: uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF
27. Parameter Settings for User Entity Instance: slib_clock_div:inst2
28. scfifo Parameter Settings by Entity Instance
29. Analysis & Synthesis Messages
30. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Feb 17 23:02:31 2009 ;
; Quartus II Version ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name ; UART16750 ;
; Top-level Entity Name ; UART16750 ;
; Family ; Cyclone II ;
; Total logic elements ; 417 ;
; Total combinational functions ; 417 ;
; Dedicated logic registers ; 293 ;
; Total registers ; 293 ;
; Total pins ; 36 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 1,216 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C5F256C6 ; ;
; Top-level entity name ; UART16750 ; UART16750 ;
; Family name ; Cyclone II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+--------------------------------------------------------------+--------------------+--------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
; ../../../rtl/vhdl/uart_transmitter.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_transmitter.vhd ;
; ../../../rtl/vhdl/slib_clock_div.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_clock_div.vhd ;
; ../../../rtl/vhdl/slib_counter.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_counter.vhd ;
; ../../../rtl/vhdl/slib_edge_detect.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_edge_detect.vhd ;
; ../../../rtl/vhdl/slib_fifo_cyclone2.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_fifo_cyclone2.vhd ;
; ../../../rtl/vhdl/slib_input_filter.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_input_filter.vhd ;
; ../../../rtl/vhdl/slib_input_sync.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_input_sync.vhd ;
; ../../../rtl/vhdl/slib_mv_filter.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_mv_filter.vhd ;
; ../../../rtl/vhdl/uart_16750.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_16750.vhd ;
; ../../../rtl/vhdl/uart_baudgen.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_baudgen.vhd ;
; ../../../rtl/vhdl/uart_interrupt.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_interrupt.vhd ;
; ../../../rtl/vhdl/uart_receiver.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_receiver.vhd ;
; UART16750.bdf ; yes ; User Block Diagram/Schematic File ; R:/uart16750/syn/Altera/CycloneII/UART16750.bdf ;
; scfifo.tdf ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/scfifo.tdf ;
; a_regfifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_regfifo.inc ;
; a_dpfifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_dpfifo.inc ;
; a_i2fifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_i2fifo.inc ;
; a_fffifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_fffifo.inc ;
; a_f2fifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_f2fifo.inc ;
; aglobal80.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/aglobal80.inc ;
; db/scfifo_an31.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/scfifo_an31.tdf ;
; db/a_dpfifo_te31.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/a_dpfifo_te31.tdf ;
; db/altsyncram_t681.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/altsyncram_t681.tdf ;
; db/cntr_c5b.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/cntr_c5b.tdf ;
; db/cntr_p57.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/cntr_p57.tdf ;
; db/cntr_d5b.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/cntr_d5b.tdf ;
; db/scfifo_ko31.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/scfifo_ko31.tdf ;
; db/a_dpfifo_7g31.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/a_dpfifo_7g31.tdf ;
; db/altsyncram_h981.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/altsyncram_h981.tdf ;
+------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements ; 417 ;
; ; ;
; Total combinational functions ; 417 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 223 ;
; -- 3 input functions ; 72 ;
; -- <=2 input functions ; 122 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 348 ;
; -- arithmetic mode ; 69 ;
; ; ;
; Total registers ; 293 ;
; -- Dedicated logic registers ; 293 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 36 ;
; Total memory bits ; 1216 ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 312 ;
; Total fan-out ; 2682 ;
; Average fan-out ; 3.51 ;
+---------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+---------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |UART16750 ; 417 (1) ; 293 (3) ; 1216 ; 0 ; 0 ; 0 ; 36 ; 0 ; |UART16750 ; work ;
; |slib_clock_div:inst2| ; 9 (9) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|slib_clock_div:inst2 ; work ;
; |uart_16750:inst| ; 407 (150) ; 284 (120) ; 1216 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst ; work ;
; |slib_clock_div:UART_BG2| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_clock_div:UART_BG2 ; work ;
; |slib_edge_detect:UART_BIDET| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_BIDET ; work ;
; |slib_edge_detect:UART_ED_CTS| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_CTS ; work ;
; |slib_edge_detect:UART_ED_DCD| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_DCD ; work ;
; |slib_edge_detect:UART_ED_DSR| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_DSR ; work ;
; |slib_edge_detect:UART_ED_READ| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_READ ; work ;
; |slib_edge_detect:UART_ED_RI| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_RI ; work ;
; |slib_edge_detect:UART_ED_WRITE| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_WRITE ; work ;
; |slib_edge_detect:UART_FEDET| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_FEDET ; work ;
; |slib_edge_detect:UART_IIC_THRE_ED| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_IIC_THRE_ED ; work ;
; |slib_edge_detect:UART_PEDET| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_PEDET ; work ;
; |slib_edge_detect:UART_RCLK| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_RCLK ; work ;
; |slib_fifo:UART_RXFF| ; 49 (0) ; 29 (0) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF ; work ;
; |scfifo:scfifo_component| ; 49 (0) ; 29 (0) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component ; work ;
; |scfifo_ko31:auto_generated| ; 49 (0) ; 29 (0) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated ; work ;
; |a_dpfifo_7g31:dpfifo| ; 49 (29) ; 29 (12) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo ; work ;
; |altsyncram_h981:FIFOram| ; 0 (0) ; 0 (0) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram ; work ;
; |cntr_c5b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb ; work ;
; |cntr_d5b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr ; work ;
; |cntr_p57:usedw_counter| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter ; work ;
; |slib_fifo:UART_TXFF| ; 50 (0) ; 29 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF ; work ;
; |scfifo:scfifo_component| ; 50 (0) ; 29 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component ; work ;
; |scfifo_an31:auto_generated| ; 50 (0) ; 29 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated ; work ;
; |a_dpfifo_te31:dpfifo| ; 50 (30) ; 29 (12) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo ; work ;
; |altsyncram_t681:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram ; work ;
; |cntr_c5b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb ; work ;
; |cntr_d5b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr ; work ;
; |cntr_p57:usedw_counter| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter ; work ;
; |slib_input_filter:UART_IF_CTS| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_CTS ; work ;
; |slib_input_filter:UART_IF_DCD| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DCD ; work ;
; |slib_input_filter:UART_IF_DSR| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DSR ; work ;
; |slib_input_filter:UART_IF_RI| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_RI ; work ;
; |slib_input_sync:UART_IS_CTS| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_CTS ; work ;
; |slib_input_sync:UART_IS_DCD| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_DCD ; work ;
; |slib_input_sync:UART_IS_DSR| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_DSR ; work ;
; |slib_input_sync:UART_IS_RI| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_RI ; work ;
; |slib_input_sync:UART_IS_SIN| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_SIN ; work ;
; |uart_baudgen:UART_BG16| ; 27 (27) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_baudgen:UART_BG16 ; work ;
; |uart_interrupt:UART_IIC| ; 12 (12) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_interrupt:UART_IIC ; work ;
; |uart_receiver:UART_RX| ; 66 (47) ; 32 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_receiver:UART_RX ; work ;
; |slib_counter:RX_BRC| ; 10 (10) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC ; work ;
; |slib_mv_filter:RX_MVF| ; 9 (9) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF ; work ;
; |uart_transmitter:UART_TX| ; 34 (34) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_transmitter:UART_TX ; work ;
+---------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 11 ; 64 ; 11 ; 704 ; None ;
; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ;
+------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
Encoding Type: One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |UART16750|uart_16750:inst|\UART_TXPROC:State ;
+----------------------------+--------------------------+--------------------------+----------------------------+-------------------------+
; Name ; \UART_TXPROC:State.txend ; \UART_TXPROC:State.txrun ; \UART_TXPROC:State.txstart ; \UART_TXPROC:State.idle ;
+----------------------------+--------------------------+--------------------------+----------------------------+-------------------------+
; \UART_TXPROC:State.idle ; 0 ; 0 ; 0 ; 0 ;
; \UART_TXPROC:State.txstart ; 0 ; 0 ; 1 ; 1 ;
; \UART_TXPROC:State.txrun ; 0 ; 1 ; 0 ; 1 ;
; \UART_TXPROC:State.txend ; 1 ; 0 ; 0 ; 1 ;
+----------------------------+--------------------------+--------------------------+----------------------------+-------------------------+
Encoding Type: One-Hot
+---------------------------------------------------------------------------------------------------+
; State Machine - |UART16750|uart_16750:inst|uart_receiver:UART_RX|CState ;
+--------------+--------------+-------------+------------+-------------+--------------+-------------+
; Name ; CState.mwait ; CState.stop ; CState.par ; CState.data ; CState.start ; CState.idle ;
+--------------+--------------+-------------+------------+-------------+--------------+-------------+
; CState.idle ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; CState.start ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; CState.data ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; CState.par ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; CState.stop ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; CState.mwait ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+--------------+--------------+-------------+------------+-------------+--------------+-------------+
Encoding Type: One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState ;
+--------------+--------------+-------------+------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+--------------+-------------+
; Name ; CState.stop2 ; CState.stop ; CState.par ; CState.bit7 ; CState.bit6 ; CState.bit5 ; CState.bit4 ; CState.bit3 ; CState.bit2 ; CState.bit1 ; CState.bit0 ; CState.start ; CState.idle ;
+--------------+--------------+-------------+------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+--------------+-------------+
; CState.idle ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; CState.start ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; CState.bit0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; CState.bit1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; CState.bit2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; CState.bit3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; CState.bit4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; CState.bit5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; CState.bit6 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; CState.bit7 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; CState.par ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; CState.stop ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; CState.stop2 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+--------------+--------------+-------------+------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+--------------+-------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 293 ;
; Number of registers using Synchronous Clear ; 42 ;
; Number of registers using Synchronous Load ; 34 ;
; Number of registers using Asynchronous Clear ; 232 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 120 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------------+
; Inverted Register Statistics ;
+-------------------------------------------------+---------+
; Inverted Register ; Fan out ;
+-------------------------------------------------+---------+
; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; 2 ;
; Total number of inverted registers = 1 ; ;
+-------------------------------------------------+---------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+
; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ;
; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[0] ;
; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[1] ;
; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |UART16750|uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ;
; 3:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |UART16750|uart_16750:inst|iFECounter[5] ;
; 4:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState~29 ;
; 10:1 ; 2 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |UART16750|uart_16750:inst|Mux0 ;
; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |UART16750|uart_16750:inst|Mux5 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_CTS ;
+----------------+-------+-------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------------------------------------+
; size ; 2 ; Signed Integer ;
+----------------+-------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_DSR ;
+----------------+-------+-------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------------------------------------+
; size ; 2 ; Signed Integer ;
+----------------+-------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_DCD ;
+----------------+-------+-------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------------------------------------+
; size ; 2 ; Signed Integer ;
+----------------+-------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_RI ;
+----------------+-------+------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------------------------+
; size ; 2 ; Signed Integer ;
+----------------+-------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|slib_clock_div:UART_BG2 ;
+----------------+-------+-------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------------------------------+
; ratio ; 8 ; Signed Integer ;
+----------------+-------+-------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_TXFF ;
+----------------+-------+---------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+---------------------------------------------------------+
; width ; 8 ; Signed Integer ;
; size_e ; 6 ; Signed Integer ;
+----------------+-------+---------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------+-------------+------------------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; lpm_width ; 8 ; Signed Integer ;
; LPM_NUMWORDS ; 64 ; Signed Integer ;
; LPM_WIDTHU ; 6 ; Signed Integer ;
; LPM_SHOWAHEAD ; ON ; Untyped ;
; UNDERFLOW_CHECKING ; ON ; Untyped ;
; OVERFLOW_CHECKING ; ON ; Untyped ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ;
; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ;
; ALMOST_FULL_VALUE ; 0 ; Untyped ;
; ALMOST_EMPTY_VALUE ; 0 ; Untyped ;
; USE_EAB ; ON ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; CBXI_PARAMETER ; scfifo_an31 ; Untyped ;
+-------------------------+-------------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_RXFF ;
+----------------+-------+---------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+---------------------------------------------------------+
; width ; 11 ; Signed Integer ;
; size_e ; 6 ; Signed Integer ;
+----------------+-------+---------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------+-------------+------------------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; lpm_width ; 11 ; Signed Integer ;
; LPM_NUMWORDS ; 64 ; Signed Integer ;
; LPM_WIDTHU ; 6 ; Signed Integer ;
; LPM_SHOWAHEAD ; ON ; Untyped ;
; UNDERFLOW_CHECKING ; ON ; Untyped ;
; OVERFLOW_CHECKING ; ON ; Untyped ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ;
; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ;
; ALMOST_FULL_VALUE ; 0 ; Untyped ;
; ALMOST_EMPTY_VALUE ; 0 ; Untyped ;
; USE_EAB ; ON ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; CBXI_PARAMETER ; scfifo_ko31 ; Untyped ;
+-------------------------+-------------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC ;
+----------------+-------+-------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------------------------------------------------+
; width ; 4 ; Signed Integer ;
+----------------+-------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF ;
+----------------+-------+---------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+---------------------------------------------------------------------------------+
; width ; 4 ; Signed Integer ;
; threshold ; 10 ; Signed Integer ;
+----------------+-------+---------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: slib_clock_div:inst2 ;
+----------------+-------+------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------+
; ratio ; 18 ; Untyped ;
+----------------+-------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance ;
+----------------------------+-------------------------------------------------------------+
; Name ; Value ;
+----------------------------+-------------------------------------------------------------+
; Number of entity instances ; 2 ;
; Entity Instance ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component ;
; -- FIFO Type ; Single Clock ;
; -- lpm_width ; 8 ;
; -- LPM_NUMWORDS ; 64 ;
; -- LPM_SHOWAHEAD ; ON ;
; -- USE_EAB ; ON ;
; Entity Instance ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component ;
; -- FIFO Type ; Single Clock ;
; -- lpm_width ; 11 ;
; -- LPM_NUMWORDS ; 64 ;
; -- LPM_SHOWAHEAD ; ON ;
; -- USE_EAB ; ON ;
+----------------------------+-------------------------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
Info: Processing started: Tue Feb 17 23:02:25 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UART16750 -c UART16750
Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/uart_transmitter.vhd
Info: Found design unit 1: uart_transmitter-rtl
Info: Found entity 1: uart_transmitter
Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_clock_div.vhd
Info: Found design unit 1: slib_clock_div-rtl
Info: Found entity 1: slib_clock_div
Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_counter.vhd
Info: Found design unit 1: slib_counter-rtl
Info: Found entity 1: slib_counter
Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_edge_detect.vhd
Info: Found design unit 1: slib_edge_detect-rtl
Info: Found entity 1: slib_edge_detect
Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_fifo_cyclone2.vhd
Info: Found design unit 1: slib_fifo-altera
Info: Found entity 1: slib_fifo
Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_input_filter.vhd
Info: Found design unit 1: slib_input_filter-rtl
Info: Found entity 1: slib_input_filter
Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_input_sync.vhd
Info: Found design unit 1: slib_input_sync-rtl
Info: Found entity 1: slib_input_sync
Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_mv_filter.vhd
Info: Found design unit 1: slib_mv_filter-rtl
Info: Found entity 1: slib_mv_filter
Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/uart_16750.vhd
Info: Found design unit 1: uart_16750-rtl
Info: Found entity 1: uart_16750
Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/uart_baudgen.vhd
Info: Found design unit 1: uart_baudgen-rtl
Info: Found entity 1: uart_baudgen
Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/uart_interrupt.vhd
Info: Found design unit 1: uart_interrupt-rtl
Info: Found entity 1: uart_interrupt
Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/uart_receiver.vhd
Info: Found design unit 1: uart_receiver-rtl
Info: Found entity 1: uart_receiver
Info: Found 1 design units, including 1 entities, in source file UART16750.bdf
Info: Found entity 1: UART16750
Info: Elaborating entity "UART16750" for the top level hierarchy
Info: Elaborating entity "uart_16750" for hierarchy "uart_16750:inst"
Info: Elaborating entity "slib_edge_detect" for hierarchy "uart_16750:inst|slib_edge_detect:UART_ED_WRITE"
Info: Elaborating entity "slib_input_sync" for hierarchy "uart_16750:inst|slib_input_sync:UART_IS_SIN"
Info: Elaborating entity "slib_input_filter" for hierarchy "uart_16750:inst|slib_input_filter:UART_IF_CTS"
Info: Elaborating entity "uart_interrupt" for hierarchy "uart_16750:inst|uart_interrupt:UART_IIC"
Info: Elaborating entity "uart_baudgen" for hierarchy "uart_16750:inst|uart_baudgen:UART_BG16"
Info: Elaborating entity "slib_clock_div" for hierarchy "uart_16750:inst|slib_clock_div:UART_BG2"
Info: Elaborating entity "slib_fifo" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF"
Info: Elaborating entity "scfifo" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component"
Info: Elaborated megafunction instantiation "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component"
Info: Instantiated megafunction "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component" with the following parameter:
Info: Parameter "add_ram_output_register" = "OFF"
Info: Parameter "intended_device_family" = "Cyclone II"
Info: Parameter "lpm_numwords" = "64"
Info: Parameter "lpm_showahead" = "ON"
Info: Parameter "lpm_type" = "scfifo"
Info: Parameter "lpm_width" = "8"
Info: Parameter "lpm_widthu" = "6"
Info: Parameter "overflow_checking" = "ON"
Info: Parameter "underflow_checking" = "ON"
Info: Parameter "use_eab" = "ON"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_an31.tdf
Info: Found entity 1: scfifo_an31
Info: Elaborating entity "scfifo_an31" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_te31.tdf
Info: Found entity 1: a_dpfifo_te31
Info: Elaborating entity "a_dpfifo_te31" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_t681.tdf
Info: Found entity 1: altsyncram_t681
Info: Elaborating entity "altsyncram_t681" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/cntr_c5b.tdf
Info: Found entity 1: cntr_c5b
Info: Elaborating entity "cntr_c5b" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb"
Info: Found 1 design units, including 1 entities, in source file db/cntr_p57.tdf
Info: Found entity 1: cntr_p57
Info: Elaborating entity "cntr_p57" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter"
Info: Found 1 design units, including 1 entities, in source file db/cntr_d5b.tdf
Info: Found entity 1: cntr_d5b
Info: Elaborating entity "cntr_d5b" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr"
Info: Elaborating entity "slib_fifo" for hierarchy "uart_16750:inst|slib_fifo:UART_RXFF"
Info: Elaborating entity "scfifo" for hierarchy "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component"
Info: Elaborated megafunction instantiation "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component"
Info: Instantiated megafunction "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component" with the following parameter:
Info: Parameter "add_ram_output_register" = "OFF"
Info: Parameter "intended_device_family" = "Cyclone II"
Info: Parameter "lpm_numwords" = "64"
Info: Parameter "lpm_showahead" = "ON"
Info: Parameter "lpm_type" = "scfifo"
Info: Parameter "lpm_width" = "11"
Info: Parameter "lpm_widthu" = "6"
Info: Parameter "overflow_checking" = "ON"
Info: Parameter "underflow_checking" = "ON"
Info: Parameter "use_eab" = "ON"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_ko31.tdf
Info: Found entity 1: scfifo_ko31
Info: Elaborating entity "scfifo_ko31" for hierarchy "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_7g31.tdf
Info: Found entity 1: a_dpfifo_7g31
Info: Elaborating entity "a_dpfifo_7g31" for hierarchy "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_h981.tdf
Info: Found entity 1: altsyncram_h981
Info: Elaborating entity "altsyncram_h981" for hierarchy "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram"
Info: Elaborating entity "uart_transmitter" for hierarchy "uart_16750:inst|uart_transmitter:UART_TX"
Info: Elaborating entity "uart_receiver" for hierarchy "uart_16750:inst|uart_receiver:UART_RX"
Info: Elaborating entity "slib_counter" for hierarchy "uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC"
Info: Elaborating entity "slib_mv_filter" for hierarchy "uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF"
Info: Elaborating entity "slib_clock_div" for hierarchy "slib_clock_div:inst2"
Info: State machine "|UART16750|uart_16750:inst|\UART_TXPROC:State" contains 4 states
Info: State machine "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState" contains 6 states
Info: State machine "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState" contains 13 states
Info: Selected Auto state machine encoding method for state machine "|UART16750|uart_16750:inst|\UART_TXPROC:State"
Info: Encoding result for state machine "|UART16750|uart_16750:inst|\UART_TXPROC:State"
Info: Completed encoding using 4 state bits
Info: Encoded state bit "uart_16750:inst|\UART_TXPROC:State.txend"
Info: Encoded state bit "uart_16750:inst|\UART_TXPROC:State.txrun"
Info: Encoded state bit "uart_16750:inst|\UART_TXPROC:State.txstart"
Info: Encoded state bit "uart_16750:inst|\UART_TXPROC:State.idle"
Info: State "|UART16750|uart_16750:inst|\UART_TXPROC:State.idle" uses code string "0000"
Info: State "|UART16750|uart_16750:inst|\UART_TXPROC:State.txstart" uses code string "0011"
Info: State "|UART16750|uart_16750:inst|\UART_TXPROC:State.txrun" uses code string "0101"
Info: State "|UART16750|uart_16750:inst|\UART_TXPROC:State.txend" uses code string "1001"
Info: Selected Auto state machine encoding method for state machine "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState"
Info: Encoding result for state machine "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState"
Info: Completed encoding using 6 state bits
Info: Encoded state bit "uart_16750:inst|uart_receiver:UART_RX|CState.mwait"
Info: Encoded state bit "uart_16750:inst|uart_receiver:UART_RX|CState.stop"
Info: Encoded state bit "uart_16750:inst|uart_receiver:UART_RX|CState.par"
Info: Encoded state bit "uart_16750:inst|uart_receiver:UART_RX|CState.data"
Info: Encoded state bit "uart_16750:inst|uart_receiver:UART_RX|CState.start"
Info: Encoded state bit "uart_16750:inst|uart_receiver:UART_RX|CState.idle"
Info: State "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState.idle" uses code string "000000"
Info: State "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState.start" uses code string "000011"
Info: State "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState.data" uses code string "000101"
Info: State "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState.par" uses code string "001001"
Info: State "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState.stop" uses code string "010001"
Info: State "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState.mwait" uses code string "100001"
Info: Selected Auto state machine encoding method for state machine "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState"
Info: Encoding result for state machine "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState"
Info: Completed encoding using 13 state bits
Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.stop2"
Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.stop"
Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.par"
Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit7"
Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit6"
Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit5"
Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit4"
Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit3"
Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit2"
Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit1"
Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit0"
Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.start"
Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.idle"
Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.idle" uses code string "0000000000000"
Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.start" uses code string "0000000000011"
Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit0" uses code string "0000000000101"
Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit1" uses code string "0000000001001"
Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit2" uses code string "0000000010001"
Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit3" uses code string "0000000100001"
Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit4" uses code string "0000001000001"
Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit5" uses code string "0000010000001"
Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit6" uses code string "0000100000001"
Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit7" uses code string "0001000000001"
Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.par" uses code string "0010000000001"
Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.stop" uses code string "0100000000001"
Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.stop2" uses code string "1000000000001"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Generated suppressed messages file R:/uart16750/syn/Altera/CycloneII/UART16750.map.smsg
Info: Implemented 584 device resources after synthesis - the final resource count might be different
Info: Implemented 21 input pins
Info: Implemented 15 output pins
Info: Implemented 529 logic cells
Info: Implemented 19 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 182 megabytes
Info: Processing ended: Tue Feb 17 23:02:31 2009
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:06
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in R:/uart16750/syn/Altera/CycloneII/UART16750.map.smsg.