Subversion Repositories uart16750

# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#               UART16750_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#               assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C5F256C6
set_global_assignment -name TOP_LEVEL_ENTITY UART16750
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:40:30  JANUARY 16, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 8.0
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz"
set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id CLK
set_instance_assignment -name CLOCK_SETTINGS CLK -to CLK
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_G13 -to A[0]
set_location_assignment PIN_F15 -to A[2]
set_location_assignment PIN_F16 -to A[1]
set_location_assignment PIN_G12 -to CS
set_location_assignment PIN_M15 -to CTSN
set_location_assignment PIN_M16 -to DCDN
set_location_assignment PIN_E16 -to DDIS
set_location_assignment PIN_A14 -to DIN[7]
set_location_assignment PIN_A13 -to DIN[6]
set_location_assignment PIN_A12 -to DIN[5]
set_location_assignment PIN_A11 -to DIN[4]
set_location_assignment PIN_B14 -to DIN[3]
set_location_assignment PIN_B13 -to DIN[2]
set_location_assignment PIN_B12 -to DIN[1]
set_location_assignment PIN_B11 -to DIN[0]
set_location_assignment PIN_R11 -to DOUT[7]
set_location_assignment PIN_R12 -to DOUT[6]
set_location_assignment PIN_R13 -to DOUT[5]
set_location_assignment PIN_R14 -to DOUT[4]
set_location_assignment PIN_T11 -to DOUT[3]
set_location_assignment PIN_T12 -to DOUT[2]
set_location_assignment PIN_T13 -to DOUT[1]
set_location_assignment PIN_T14 -to DOUT[0]
set_location_assignment PIN_L14 -to DSRN
set_location_assignment PIN_L15 -to DTRN
set_location_assignment PIN_D16 -to INT
set_location_assignment PIN_N16 -to OUT1N
set_location_assignment PIN_N15 -to OUT2N
set_location_assignment PIN_D15 -to RD
set_location_assignment PIN_L16 -to RIN
set_location_assignment PIN_K15 -to RTSN
set_location_assignment PIN_G15 -to SIN
set_location_assignment PIN_K16 -to SOUT
set_location_assignment PIN_E14 -to WR
set_location_assignment PIN_H15 -to CLK
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3
set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to DDIS
set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to DOUT
set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to DTRN
set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to INT
set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to OUT1N
set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to OUT2N
set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to RTSN
set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to SOUT
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name TSU_REQUIREMENT "10 ns"
set_global_assignment -name TCO_REQUIREMENT "15 ns"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, S103, S104, D101, D102, D103, H101, H102, M101, M102, M103, M104, M105"
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_location_assignment PIN_G16 -to RSTN
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/uart_transmitter.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_clock_div.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_counter.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_edge_detect.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_fifo_cyclone2.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_input_filter.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_input_sync.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_mv_filter.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/uart_16750.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/uart_baudgen.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/uart_interrupt.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/uart_receiver.vhd
set_global_assignment -name BDF_FILE UART16750.bdf