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[/] [uart16750/] [trunk/] [syn/] [Altera/] [CycloneII/] [UART16750.tan.rpt] - Rev 17
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Classic Timing Analyzer report for UART16750Tue Feb 17 23:02:39 2009Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version---------------------; Table of Contents ;---------------------1. Legal Notice2. Timing Analyzer Summary3. Timing Analyzer Settings4. Clock Settings Summary5. Clock Setup: 'CLK'6. Clock Hold: 'CLK'7. tsu8. tco9. tpd10. th11. Timing Analyzer Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2008 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Timing Analyzer Summary ;+------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;+------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+; Worst-case tsu ; 2.580 ns ; 10.000 ns ; 7.420 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; -- ; CLK ; 0 ;; Worst-case tco ; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[3] ; CLK ; -- ; 0 ;; Worst-case tpd ; N/A ; None ; 14.563 ns ; A[1] ; DOUT[3] ; -- ; -- ; 0 ;; Worst-case th ; N/A ; None ; -2.602 ns ; WR ; uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd ; -- ; CLK ; 0 ;; Clock Setup: 'CLK' ; 22.036 ns ; 33.33 MHz ( period = 30.003 ns ) ; 125.52 MHz ( period = 7.967 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 0 ;; Clock Hold: 'CLK' ; 0.391 ns ; 33.33 MHz ( period = 30.003 ns ) ; N/A ; uart_16750:inst|iLSR_FIFOERR ; uart_16750:inst|iLSR_FIFOERR ; CLK ; CLK ; 0 ;; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;+------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+--------------++-------------------------------------------------------------------------------------------------------------------------+; Timing Analyzer Settings ;+---------------------------------------------------------------------+--------------------+------+---------+-------------+; Option ; Setting ; From ; To ; Entity Name ;+---------------------------------------------------------------------+--------------------+------+---------+-------------+; Device Name ; EP2C5F256C6 ; ; ; ;; Timing Models ; Final ; ; ; ;; Default hold multicycle ; Same as Multicycle ; ; ; ;; Cut paths between unrelated clock domains ; On ; ; ; ;; Cut off read during write signal paths ; On ; ; ; ;; Cut off feedback from I/O pins ; On ; ; ; ;; Report Combined Fast/Slow Timing ; Off ; ; ; ;; tsu Requirement ; 10 ns ; ; ; ;; tco Requirement ; 15 ns ; ; ; ;; fmax Requirement ; 33.33 MHz ; ; ; ;; Ignore Clock Settings ; Off ; ; ; ;; Analyze latches as synchronous elements ; On ; ; ; ;; Enable Recovery/Removal analysis ; Off ; ; ; ;; Enable Clock Latency ; Off ; ; ; ;; Use TimeQuest Timing Analyzer ; Off ; ; ; ;; Number of source nodes to report per destination node ; 10 ; ; ; ;; Number of destination nodes to report ; 10 ; ; ; ;; Number of paths to report ; 200 ; ; ; ;; Report Minimum Timing Checks ; Off ; ; ; ;; Use Fast Timing Models ; Off ; ; ; ;; Report IO Paths Separately ; Off ; ; ; ;; Perform Multicorner Analysis ; On ; ; ; ;; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;; Clock Settings ; CLK ; ; CLK ; ;; Output Pin Load ; 10 ; ; DDIS ; ;; Output Pin Load ; 10 ; ; INT ; ;; Output Pin Load ; 10 ; ; OUT1N ; ;; Output Pin Load ; 10 ; ; OUT2N ; ;; Output Pin Load ; 10 ; ; RTSN ; ;; Output Pin Load ; 10 ; ; DTRN ; ;; Output Pin Load ; 10 ; ; SOUT ; ;; Output Pin Load ; 10 ; ; DOUT[7] ; ;; Output Pin Load ; 10 ; ; DOUT[6] ; ;; Output Pin Load ; 10 ; ; DOUT[5] ; ;; Output Pin Load ; 10 ; ; DOUT[4] ; ;; Output Pin Load ; 10 ; ; DOUT[3] ; ;; Output Pin Load ; 10 ; ; DOUT[2] ; ;; Output Pin Load ; 10 ; ; DOUT[1] ; ;; Output Pin Load ; 10 ; ; DOUT[0] ; ;+---------------------------------------------------------------------+--------------------+------+---------+-------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clock Settings Summary ;+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+; CLK ; CLK ; User Pin ; 33.33 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clock Setup: 'CLK' ;+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+; 22.036 ns ; 125.52 MHz ( period = 7.967 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.752 ns ;; 22.054 ns ; 125.80 MHz ( period = 7.949 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.734 ns ;; 22.107 ns ; 126.65 MHz ( period = 7.896 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.681 ns ;; 22.125 ns ; 126.94 MHz ( period = 7.878 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.663 ns ;; 22.178 ns ; 127.80 MHz ( period = 7.825 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.610 ns ;; 22.196 ns ; 128.09 MHz ( period = 7.807 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.592 ns ;; 22.206 ns ; 128.25 MHz ( period = 7.797 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.582 ns ;; 22.249 ns ; 128.97 MHz ( period = 7.754 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.539 ns ;; 22.267 ns ; 129.27 MHz ( period = 7.736 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.521 ns ;; 22.277 ns ; 129.43 MHz ( period = 7.726 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.511 ns ;; 22.348 ns ; 130.63 MHz ( period = 7.655 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.440 ns ;; 22.405 ns ; 131.61 MHz ( period = 7.598 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.333 ns ;; 22.405 ns ; 131.61 MHz ( period = 7.598 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.333 ns ;; 22.405 ns ; 131.61 MHz ( period = 7.598 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.333 ns ;; 22.405 ns ; 131.61 MHz ( period = 7.598 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.333 ns ;; 22.405 ns ; 131.61 MHz ( period = 7.598 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.333 ns ;; 22.405 ns ; 131.61 MHz ( period = 7.598 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.333 ns ;; 22.419 ns ; 131.86 MHz ( period = 7.584 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.369 ns ;; 22.476 ns ; 132.86 MHz ( period = 7.527 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[5] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.262 ns ;; 22.476 ns ; 132.86 MHz ( period = 7.527 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[5] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.262 ns ;; 22.476 ns ; 132.86 MHz ( period = 7.527 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[5] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.262 ns ;; 22.476 ns ; 132.86 MHz ( period = 7.527 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[5] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.262 ns ;; 22.476 ns ; 132.86 MHz ( period = 7.527 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[5] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.262 ns ;; 22.476 ns ; 132.86 MHz ( period = 7.527 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[5] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.262 ns ;; 22.547 ns ; 134.12 MHz ( period = 7.456 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[4] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.191 ns ;; 22.547 ns ; 134.12 MHz ( period = 7.456 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[4] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.191 ns ;; 22.547 ns ; 134.12 MHz ( period = 7.456 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[4] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.191 ns ;; 22.547 ns ; 134.12 MHz ( period = 7.456 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[4] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.191 ns ;; 22.547 ns ; 134.12 MHz ( period = 7.456 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[4] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.191 ns ;; 22.547 ns ; 134.12 MHz ( period = 7.456 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[4] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.191 ns ;; 22.618 ns ; 135.41 MHz ( period = 7.385 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.120 ns ;; 22.618 ns ; 135.41 MHz ( period = 7.385 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.120 ns ;; 22.618 ns ; 135.41 MHz ( period = 7.385 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.120 ns ;; 22.618 ns ; 135.41 MHz ( period = 7.385 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.120 ns ;; 22.618 ns ; 135.41 MHz ( period = 7.385 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.120 ns ;; 22.618 ns ; 135.41 MHz ( period = 7.385 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.120 ns ;; 22.632 ns ; 135.67 MHz ( period = 7.371 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.156 ns ;; 22.650 ns ; 136.00 MHz ( period = 7.353 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.138 ns ;; 22.689 ns ; 136.72 MHz ( period = 7.314 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[2] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.049 ns ;; 22.689 ns ; 136.72 MHz ( period = 7.314 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[2] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.049 ns ;; 22.689 ns ; 136.72 MHz ( period = 7.314 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[2] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.049 ns ;; 22.689 ns ; 136.72 MHz ( period = 7.314 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[2] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.049 ns ;; 22.689 ns ; 136.72 MHz ( period = 7.314 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[2] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.049 ns ;; 22.689 ns ; 136.72 MHz ( period = 7.314 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[2] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.049 ns ;; 22.707 ns ; 137.06 MHz ( period = 7.296 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.081 ns ;; 22.733 ns ; 137.55 MHz ( period = 7.270 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.781 ns ; 7.048 ns ;; 22.778 ns ; 138.41 MHz ( period = 7.225 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.010 ns ;; 22.802 ns ; 138.87 MHz ( period = 7.201 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.986 ns ;; 22.804 ns ; 138.91 MHz ( period = 7.199 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.781 ns ; 6.977 ns ;; 22.820 ns ; 139.22 MHz ( period = 7.183 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.968 ns ;; 22.840 ns ; 139.61 MHz ( period = 7.163 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.943 ns ;; 22.849 ns ; 139.78 MHz ( period = 7.154 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.939 ns ;; 22.875 ns ; 140.29 MHz ( period = 7.128 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.781 ns ; 6.906 ns ;; 22.891 ns ; 140.61 MHz ( period = 7.112 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.897 ns ;; 22.911 ns ; 141.00 MHz ( period = 7.092 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.872 ns ;; 22.920 ns ; 141.18 MHz ( period = 7.083 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.868 ns ;; 22.946 ns ; 141.70 MHz ( period = 7.057 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.781 ns ; 6.835 ns ;; 22.960 ns ; 141.98 MHz ( period = 7.043 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.828 ns ;; 22.962 ns ; 142.03 MHz ( period = 7.041 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.826 ns ;; 22.982 ns ; 142.43 MHz ( period = 7.021 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.801 ns ;; 23.031 ns ; 143.43 MHz ( period = 6.972 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.757 ns ;; 23.033 ns ; 143.47 MHz ( period = 6.970 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.755 ns ;; 23.053 ns ; 143.88 MHz ( period = 6.950 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.730 ns ;; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ;; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ;; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ;; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ;; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ;; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ;; 23.102 ns ; 144.91 MHz ( period = 6.901 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.686 ns ;; 23.147 ns ; 145.86 MHz ( period = 6.856 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.641 ns ;; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ;; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ;; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ;; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ;; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ;; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ;; 23.173 ns ; 146.41 MHz ( period = 6.830 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.615 ns ;; 23.218 ns ; 147.38 MHz ( period = 6.785 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.570 ns ;; 23.289 ns ; 148.94 MHz ( period = 6.714 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.499 ns ;; 23.303 ns ; 149.25 MHz ( period = 6.700 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.485 ns ;; 23.329 ns ; 149.84 MHz ( period = 6.674 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.781 ns ; 6.452 ns ;; 23.360 ns ; 150.53 MHz ( period = 6.643 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.428 ns ;; 23.416 ns ; 151.81 MHz ( period = 6.587 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.372 ns ;; 23.436 ns ; 152.28 MHz ( period = 6.567 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.347 ns ;; 23.556 ns ; 155.11 MHz ( period = 6.447 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.232 ns ;; 23.616 ns ; 156.57 MHz ( period = 6.387 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 6.166 ns ;; 23.630 ns ; 156.91 MHz ( period = 6.373 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 6.162 ns ;; 23.648 ns ; 157.36 MHz ( period = 6.355 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 6.144 ns ;; 23.687 ns ; 158.33 MHz ( period = 6.316 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 6.095 ns ;; 23.695 ns ; 158.53 MHz ( period = 6.308 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 6.108 ns ;; 23.704 ns ; 158.76 MHz ( period = 6.299 ns ) ; uart_16750:inst|iLCR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.079 ns ;; 23.713 ns ; 158.98 MHz ( period = 6.290 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 6.090 ns ;; 23.743 ns ; 159.74 MHz ( period = 6.260 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.045 ns ;; 23.758 ns ; 160.13 MHz ( period = 6.245 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 6.024 ns ;; 23.775 ns ; 160.57 MHz ( period = 6.228 ns ) ; uart_16750:inst|iLCR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.008 ns ;; 23.796 ns ; 161.11 MHz ( period = 6.207 ns ) ; uart_16750:inst|iTSR[6] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 5.992 ns ;; 23.800 ns ; 161.21 MHz ( period = 6.203 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.992 ns ;; 23.829 ns ; 161.97 MHz ( period = 6.174 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 5.953 ns ;; 23.846 ns ; 162.42 MHz ( period = 6.157 ns ) ; uart_16750:inst|iLCR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 5.937 ns ;; 23.865 ns ; 162.92 MHz ( period = 6.138 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 5.938 ns ;; 23.867 ns ; 162.97 MHz ( period = 6.136 ns ) ; uart_16750:inst|iTSR[6] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 5.921 ns ;; 23.875 ns ; 163.19 MHz ( period = 6.128 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.917 ns ;; 23.875 ns ; 163.19 MHz ( period = 6.128 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.917 ns ;; 23.893 ns ; 163.67 MHz ( period = 6.110 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.899 ns ;; 23.893 ns ; 163.67 MHz ( period = 6.110 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.899 ns ;; 23.917 ns ; 164.31 MHz ( period = 6.086 ns ) ; uart_16750:inst|iLCR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 5.866 ns ;; 23.938 ns ; 164.88 MHz ( period = 6.065 ns ) ; uart_16750:inst|iTSR[6] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 5.850 ns ;; 23.942 ns ; 164.99 MHz ( period = 6.061 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.842 ns ;; 23.970 ns ; 165.76 MHz ( period = 6.033 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.769 ns ;; 23.970 ns ; 165.76 MHz ( period = 6.033 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.769 ns ;; 23.970 ns ; 165.76 MHz ( period = 6.033 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.769 ns ;; 23.970 ns ; 165.76 MHz ( period = 6.033 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.769 ns ;; 23.970 ns ; 165.76 MHz ( period = 6.033 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.769 ns ;; 23.970 ns ; 165.76 MHz ( period = 6.033 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.769 ns ;; 23.993 ns ; 166.39 MHz ( period = 6.010 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.par ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.793 ns ;; 24.009 ns ; 166.83 MHz ( period = 5.994 ns ) ; uart_16750:inst|iTSR[6] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 5.779 ns ;; 24.013 ns ; 166.94 MHz ( period = 5.990 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.771 ns ;; 24.029 ns ; 167.39 MHz ( period = 5.974 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.757 ns ;; 24.045 ns ; 167.84 MHz ( period = 5.958 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.747 ns ;; 24.045 ns ; 167.84 MHz ( period = 5.958 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.747 ns ;; 24.064 ns ; 168.38 MHz ( period = 5.939 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.par ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.722 ns ;; 24.084 ns ; 168.95 MHz ( period = 5.919 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.700 ns ;; 24.099 ns ; 169.38 MHz ( period = 5.904 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.685 ns ;; 24.100 ns ; 169.41 MHz ( period = 5.903 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.686 ns ;; 24.135 ns ; 170.42 MHz ( period = 5.868 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.par ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.651 ns ;; 24.143 ns ; 170.65 MHz ( period = 5.860 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; CLK ; CLK ; 30.003 ns ; 29.789 ns ; 5.646 ns ;; 24.155 ns ; 171.00 MHz ( period = 5.848 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.629 ns ;; 24.170 ns ; 171.44 MHz ( period = 5.833 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.614 ns ;; 24.171 ns ; 171.47 MHz ( period = 5.832 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.615 ns ;; 24.179 ns ; 171.70 MHz ( period = 5.824 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.560 ns ;; 24.179 ns ; 171.70 MHz ( period = 5.824 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.560 ns ;; 24.179 ns ; 171.70 MHz ( period = 5.824 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.560 ns ;; 24.179 ns ; 171.70 MHz ( period = 5.824 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.560 ns ;; 24.179 ns ; 171.70 MHz ( period = 5.824 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.560 ns ;; 24.179 ns ; 171.70 MHz ( period = 5.824 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.560 ns ;; 24.206 ns ; 172.50 MHz ( period = 5.797 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.par ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.580 ns ;; 24.212 ns ; 172.68 MHz ( period = 5.791 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 5.570 ns ;; 24.241 ns ; 173.55 MHz ( period = 5.762 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.543 ns ;; 24.242 ns ; 173.58 MHz ( period = 5.761 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.544 ns ;; 24.300 ns ; 175.35 MHz ( period = 5.703 ns ) ; uart_16750:inst|iLCR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 5.483 ns ;; 24.301 ns ; 175.38 MHz ( period = 5.702 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.491 ns ;; 24.312 ns ; 175.72 MHz ( period = 5.691 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.472 ns ;; 24.327 ns ; 176.18 MHz ( period = 5.676 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.785 ns ; 5.458 ns ;; 24.338 ns ; 176.52 MHz ( period = 5.665 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.448 ns ;; 24.354 ns ; 177.02 MHz ( period = 5.649 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit4 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.430 ns ;; 24.366 ns ; 177.40 MHz ( period = 5.637 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 5.437 ns ;; 24.392 ns ; 178.22 MHz ( period = 5.611 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.796 ns ; 5.404 ns ;; 24.392 ns ; 178.22 MHz ( period = 5.611 ns ) ; uart_16750:inst|iTSR[6] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 5.396 ns ;; 24.409 ns ; 178.76 MHz ( period = 5.594 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.377 ns ;; 24.414 ns ; 178.92 MHz ( period = 5.589 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.378 ns ;; 24.425 ns ; 179.28 MHz ( period = 5.578 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit4 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.359 ns ;; 24.434 ns ; 179.57 MHz ( period = 5.569 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.787 ns ; 5.353 ns ;; 24.440 ns ; 179.76 MHz ( period = 5.563 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; CLK ; CLK ; 30.003 ns ; 29.789 ns ; 5.349 ns ;; 24.463 ns ; 180.51 MHz ( period = 5.540 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.321 ns ;; 24.479 ns ; 181.03 MHz ( period = 5.524 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 5.324 ns ;; 24.480 ns ; 181.06 MHz ( period = 5.523 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.306 ns ;; 24.496 ns ; 181.59 MHz ( period = 5.507 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit4 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.288 ns ;; 24.499 ns ; 181.69 MHz ( period = 5.504 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.798 ns ; 5.299 ns ;; 24.534 ns ; 182.85 MHz ( period = 5.469 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.250 ns ;; 24.538 ns ; 182.98 MHz ( period = 5.465 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.246 ns ;; 24.546 ns ; 183.25 MHz ( period = 5.457 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.246 ns ;; 24.546 ns ; 183.25 MHz ( period = 5.457 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.246 ns ;; 24.551 ns ; 183.42 MHz ( period = 5.452 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.235 ns ;; 24.554 ns ; 183.52 MHz ( period = 5.449 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.238 ns ;; 24.567 ns ; 183.96 MHz ( period = 5.436 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit4 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.217 ns ;; 24.568 ns ; 183.99 MHz ( period = 5.435 ns ) ; uart_16750:inst|iFCR_RXTrigger[0] ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; CLK ; CLK ; 30.003 ns ; 29.790 ns ; 5.222 ns ;; 24.572 ns ; 184.13 MHz ( period = 5.431 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.785 ns ; 5.213 ns ;; 24.572 ns ; 184.13 MHz ( period = 5.431 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.785 ns ; 5.213 ns ;; 24.589 ns ; 184.71 MHz ( period = 5.414 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.par ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.197 ns ;; 24.605 ns ; 185.25 MHz ( period = 5.398 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.179 ns ;; 24.619 ns ; 185.74 MHz ( period = 5.384 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 5.184 ns ;; 24.625 ns ; 185.94 MHz ( period = 5.378 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.161 ns ;; 24.659 ns ; 187.13 MHz ( period = 5.344 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.133 ns ;; 24.659 ns ; 187.13 MHz ( period = 5.344 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.133 ns ;; 24.671 ns ; 187.55 MHz ( period = 5.332 ns ) ; uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 5.112 ns ;; 24.676 ns ; 187.72 MHz ( period = 5.327 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.108 ns ;; 24.679 ns ; 187.83 MHz ( period = 5.324 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.787 ns ; 5.108 ns ;; 24.679 ns ; 187.83 MHz ( period = 5.324 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.787 ns ; 5.108 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[15] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[12] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[10] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[11] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[9] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[8] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[5] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[6] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[14] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[7] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[13] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ;; 24.695 ns ; 188.39 MHz ( period = 5.308 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.089 ns ;; 24.721 ns ; 189.32 MHz ( period = 5.282 ns ) ; uart_16750:inst|iFCR_RXTrigger[1] ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; CLK ; CLK ; 30.003 ns ; 29.790 ns ; 5.069 ns ;; 24.741 ns ; 190.04 MHz ( period = 5.262 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.051 ns ;; 24.770 ns ; 191.09 MHz ( period = 5.233 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; uart_16750:inst|iRTS ; CLK ; CLK ; 30.003 ns ; 29.805 ns ; 5.035 ns ;; 24.786 ns ; 191.68 MHz ( period = 5.217 ns ) ; uart_16750:inst|iDLL[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[15] ; CLK ; CLK ; 30.003 ns ; 29.770 ns ; 4.984 ns ;; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clock Hold: 'CLK' ;+-----------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;+-----------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+; 0.391 ns ; uart_16750:inst|iLSR_FIFOERR ; uart_16750:inst|iLSR_FIFOERR ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|Q ; uart_16750:inst|slib_input_filter:UART_IF_DSR|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|Q ; uart_16750:inst|slib_input_filter:UART_IF_DCD|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|Q ; uart_16750:inst|slib_input_filter:UART_IF_RI|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|iLSR_BI ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|iLSR_FE ; uart_16750:inst|iLSR_FE ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|iMSR_dCTS ; uart_16750:inst|iMSR_dCTS ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|iLSR_PE ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|iLSR_OE ; uart_16750:inst|iLSR_OE ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|iMSR_dDSR ; uart_16750:inst|iMSR_dDSR ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|iMSR_dDCD ; uart_16750:inst|iMSR_dDCD ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|iMSR_TERI ; uart_16750:inst|iMSR_TERI ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|iCharTimeout ; uart_16750:inst|iCharTimeout ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|\UART_TXPROC:State.txrun ; uart_16750:inst|\UART_TXPROC:State.txrun ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[0] ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[2] ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[1] ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|Q ; uart_16750:inst|slib_input_filter:UART_IF_CTS|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|\UART_TXPROC:State.idle ; uart_16750:inst|\UART_TXPROC:State.idle ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_transmitter:UART_TX|iTx2 ; uart_16750:inst|uart_transmitter:UART_TX|iTx2 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[5] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[4] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[3] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[2] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[1] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[0] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|rd_ptr_lsb ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|rd_ptr_lsb ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|full_dff ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|full_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit6 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit6 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.data ; uart_16750:inst|uart_receiver:UART_RX|CState.data ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|iFCR_FIFO64E ; uart_16750:inst|iFCR_FIFO64E ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iParityReceived ; uart_16750:inst|uart_receiver:UART_RX|iParityReceived ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[7] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[7] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[5] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[4] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[3] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[2] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[1] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|\UART_RXPROC:State ; uart_16750:inst|\UART_RXPROC:State ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[6] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[6] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[5] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[4] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[3] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[2] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[1] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|rd_ptr_lsb ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|rd_ptr_lsb ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[0] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[0] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ;; 0.516 ns ; uart_16750:inst|slib_input_sync:UART_IS_RI|iD[0] ; uart_16750:inst|slib_input_sync:UART_IS_RI|iD[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.532 ns ;; 0.516 ns ; inst4 ; inst5 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.532 ns ;; 0.522 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.538 ns ;; 0.523 ns ; uart_16750:inst|slib_input_sync:UART_IS_RI|iD[1] ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.539 ns ;; 0.524 ns ; uart_16750:inst|slib_input_sync:UART_IS_RI|iD[1] ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.540 ns ;; 0.525 ns ; uart_16750:inst|uart_transmitter:UART_TX|\TX_FIN:iLast ; uart_16750:inst|uart_transmitter:UART_TX|iFinished ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.541 ns ;; 0.525 ns ; uart_16750:inst|iMCR[5] ; uart_16750:inst|iRTS ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.541 ns ;; 0.526 ns ; uart_16750:inst|slib_input_sync:UART_IS_DSR|iD[0] ; uart_16750:inst|slib_input_sync:UART_IS_DSR|iD[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.542 ns ;; 0.529 ns ; uart_16750:inst|iTimeoutCount[5] ; uart_16750:inst|iTimeoutCount[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.545 ns ;; 0.529 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.545 ns ;; 0.529 ns ; uart_16750:inst|uart_transmitter:UART_TX|iFinished ; uart_16750:inst|\UART_TXPROC:State.txend ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.545 ns ;; 0.529 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.545 ns ;; 0.530 ns ; uart_16750:inst|slib_input_sync:UART_IS_CTS|iD[0] ; uart_16750:inst|slib_input_sync:UART_IS_CTS|iD[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.546 ns ;; 0.531 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[15] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[15] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.547 ns ;; 0.531 ns ; uart_16750:inst|\UART_TXPROC:State.txrun ; uart_16750:inst|iTXStart ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.547 ns ;; 0.531 ns ; uart_16750:inst|uart_receiver:UART_RX|iBaudStepD ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.547 ns ;; 0.531 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[5] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.547 ns ;; 0.532 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.548 ns ;; 0.533 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.549 ns ;; 0.533 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[5] ; uart_16750:inst|iRXFIFOD[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.549 ns ;; 0.533 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[1] ; uart_16750:inst|iRXFIFOD[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.549 ns ;; 0.534 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.550 ns ;; 0.536 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.552 ns ;; 0.537 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_DSR|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.553 ns ;; 0.537 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.553 ns ;; 0.537 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[0] ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.553 ns ;; 0.538 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.554 ns ;; 0.538 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[7] ; uart_16750:inst|iRXFIFOD[7] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.554 ns ;; 0.538 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[3] ; uart_16750:inst|iRXFIFOD[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.554 ns ;; 0.538 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[2] ; uart_16750:inst|iRXFIFOD[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.554 ns ;; 0.539 ns ; slib_clock_div:inst2|iCounter[0] ; slib_clock_div:inst2|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.555 ns ;; 0.539 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[0] ; uart_16750:inst|slib_clock_div:UART_BG2|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.555 ns ;; 0.539 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|rd_ptr_lsb ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.555 ns ;; 0.540 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[0] ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.556 ns ;; 0.541 ns ; uart_16750:inst|slib_input_sync:UART_IS_CTS|iD[1] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.557 ns ;; 0.541 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[4] ; uart_16750:inst|iRXFIFOD[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.557 ns ;; 0.552 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.568 ns ;; 0.553 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[2] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.569 ns ;; 0.555 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.571 ns ;; 0.557 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[3] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.573 ns ;; 0.559 ns ; uart_16750:inst|iMCR[4] ; uart_16750:inst|DTRN ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.575 ns ;; 0.562 ns ; uart_16750:inst|iMCR[4] ; uart_16750:inst|RTSN ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.578 ns ;; 0.562 ns ; uart_16750:inst|iMCR[4] ; uart_16750:inst|slib_edge_detect:UART_ED_CTS|iDd ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.578 ns ;; 0.567 ns ; uart_16750:inst|uart_baudgen:UART_BG16|BAUDTICK ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.583 ns ;; 0.568 ns ; uart_16750:inst|uart_baudgen:UART_BG16|BAUDTICK ; uart_16750:inst|BAUDOUTN ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.584 ns ;; 0.638 ns ; uart_16750:inst|\UART_TXPROC:State.txstart ; uart_16750:inst|iTXStart ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.654 ns ;; 0.656 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit0 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit1 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.672 ns ;; 0.657 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[2] ; uart_16750:inst|slib_clock_div:UART_BG2|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.673 ns ;; 0.660 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit3 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit4 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.676 ns ;; 0.660 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit2 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit3 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.676 ns ;; 0.662 ns ; uart_16750:inst|slib_input_sync:UART_IS_SIN|iD[0] ; uart_16750:inst|slib_input_sync:UART_IS_SIN|iD[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.678 ns ;; 0.663 ns ; uart_16750:inst|iIER[3] ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.679 ns ;; 0.664 ns ; uart_16750:inst|slib_input_sync:UART_IS_DCD|iD[0] ; uart_16750:inst|slib_input_sync:UART_IS_DCD|iD[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.680 ns ;; 0.667 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[6] ; uart_16750:inst|iRXFIFOD[10] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.683 ns ;; 0.670 ns ; uart_16750:inst|uart_receiver:UART_RX|PE ; uart_16750:inst|iRXFIFOD[8] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.686 ns ;; 0.674 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[0] ; uart_16750:inst|iRXFIFOD[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.690 ns ;; 0.677 ns ; uart_16750:inst|\UART_TXPROC:State.txstart ; uart_16750:inst|iTXFIFORead ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.693 ns ;; 0.677 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[6] ; uart_16750:inst|iRXFIFOD[6] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.693 ns ;; 0.696 ns ; uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4] ; uart_16750:inst|uart_receiver:UART_RX|iBaudStepD ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.712 ns ;; 0.702 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.stop ; uart_16750:inst|iRXFIFOD[9] ; CLK ; CLK ; 0.000 ns ; 0.018 ns ; 0.720 ns ;; 0.755 ns ; slib_clock_div:inst2|iCounter[1] ; slib_clock_div:inst2|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.771 ns ;; 0.759 ns ; uart_16750:inst|\UART_TXPROC:State.txend ; uart_16750:inst|\UART_TXPROC:State.idle ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.775 ns ;; 0.765 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[7] ; uart_16750:inst|iRXFIFOD[10] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.781 ns ;; 0.770 ns ; uart_16750:inst|\UART_TXPROC:State.idle ; uart_16750:inst|\UART_TXPROC:State.txstart ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.786 ns ;; 0.778 ns ; uart_16750:inst|iTimeoutCount[5] ; uart_16750:inst|iCharTimeout ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.794 ns ;; 0.780 ns ; uart_16750:inst|iRTS ; uart_16750:inst|RTSN ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.796 ns ;; 0.795 ns ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[2] ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.811 ns ;; 0.795 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.811 ns ;; 0.797 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.813 ns ;; 0.798 ns ; uart_16750:inst|slib_edge_detect:UART_ED_DSR|iDd ; uart_16750:inst|iMSR_dDSR ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.814 ns ;; 0.799 ns ; uart_16750:inst|iTimeoutCount[0] ; uart_16750:inst|iTimeoutCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.815 ns ;; 0.799 ns ; uart_16750:inst|iTimeoutCount[3] ; uart_16750:inst|iTimeoutCount[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.815 ns ;; 0.799 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[0] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.815 ns ;; 0.799 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.815 ns ;; 0.800 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_2_dff ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_1_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.816 ns ;; 0.801 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.817 ns ;; 0.801 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.data ; uart_16750:inst|uart_receiver:UART_RX|CState.par ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.817 ns ;; 0.801 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.817 ns ;; 0.802 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[2] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.818 ns ;; 0.803 ns ; uart_16750:inst|iRTS ; uart_16750:inst|slib_edge_detect:UART_ED_CTS|iDd ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.819 ns ;; 0.804 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.820 ns ;; 0.804 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.data ; uart_16750:inst|uart_receiver:UART_RX|CState.stop ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.820 ns ;; 0.805 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_RI|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.821 ns ;; 0.805 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[1] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.821 ns ;; 0.805 ns ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.821 ns ;; 0.805 ns ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.821 ns ;; 0.806 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ;; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[11] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[11] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ;; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[4] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ;; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[9] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[9] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ;; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[2] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ;; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[14] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[14] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ;; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[7] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[7] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ;; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[13] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[13] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ;; 0.806 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ;; 0.806 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ;; 0.806 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ;; 0.806 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[3] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ;; 0.807 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|Q ; uart_16750:inst|slib_edge_detect:UART_ED_RI|iDd ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.823 ns ;; 0.808 ns ; slib_clock_div:inst2|iCounter[0] ; slib_clock_div:inst2|iCounter[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.824 ns ;; 0.809 ns ; uart_16750:inst|slib_edge_detect:UART_FEDET|iDd ; uart_16750:inst|iLSR_FE ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.825 ns ;; 0.809 ns ; uart_16750:inst|\UART_TXPROC:State.idle ; uart_16750:inst|iTXStart ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.825 ns ;; 0.809 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.825 ns ;; 0.810 ns ; uart_16750:inst|iMCR[0] ; uart_16750:inst|slib_edge_detect:UART_ED_DSR|iDd ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.826 ns ;; 0.811 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.827 ns ;; 0.812 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit6 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.828 ns ;; 0.813 ns ; slib_clock_div:inst2|iCounter[2] ; slib_clock_div:inst2|iCounter[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.829 ns ;; 0.813 ns ; uart_16750:inst|uart_baudgen:UART_BG16|BAUDTICK ; uart_16750:inst|slib_clock_div:UART_BG2|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.829 ns ;; 0.814 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_DSR|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.830 ns ;; 0.814 ns ; uart_16750:inst|iFECounter[1] ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.830 ns ;; 0.814 ns ; uart_16750:inst|iFECounter[3] ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.830 ns ;; 0.814 ns ; uart_16750:inst|iFCR_TXFIFOReset ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.830 ns ;; 0.814 ns ; uart_16750:inst|\UART_TXPROC:State.txstart ; uart_16750:inst|\UART_TXPROC:State.txrun ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.830 ns ;; 0.814 ns ; uart_16750:inst|iFCR_TXFIFOReset ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|full_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.830 ns ;; 0.815 ns ; uart_16750:inst|iFECounter[6] ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.831 ns ;; 0.816 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.832 ns ;; 0.816 ns ; uart_16750:inst|slib_input_sync:UART_IS_CTS|iD[1] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.832 ns ;; 0.816 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[1] ; uart_16750:inst|slib_clock_div:UART_BG2|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.832 ns ;; 0.817 ns ; uart_16750:inst|slib_input_sync:UART_IS_DCD|iD[1] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.833 ns ;; 0.817 ns ; uart_16750:inst|slib_input_sync:UART_IS_SIN|iD[1] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.833 ns ;; 0.817 ns ; uart_16750:inst|slib_input_sync:UART_IS_SIN|iD[1] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.833 ns ;; 0.818 ns ; uart_16750:inst|slib_input_sync:UART_IS_DCD|iD[1] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.834 ns ;; 0.818 ns ; uart_16750:inst|iMCR[0] ; uart_16750:inst|iMSR_dDSR ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.834 ns ;; 0.820 ns ; uart_16750:inst|iTimeoutCount[4] ; uart_16750:inst|iTimeoutCount[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.836 ns ;; 0.820 ns ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ ; uart_16750:inst|uart_receiver:UART_RX|iParityReceived ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.836 ns ;; 0.821 ns ; uart_16750:inst|iFECounter[0] ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.837 ns ;; 0.821 ns ; uart_16750:inst|iFCR_TXFIFOReset ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.837 ns ;; 0.821 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; uart_16750:inst|uart_transmitter:UART_TX|iTx2 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.837 ns ;; 0.822 ns ; uart_16750:inst|iFCR_TXFIFOReset ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.838 ns ;; 0.825 ns ; uart_16750:inst|slib_edge_detect:UART_ED_CTS|iDd ; uart_16750:inst|iMSR_dCTS ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.841 ns ;; 0.825 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[3] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.841 ns ;; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ;+-----------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; tsu ;+-----------------------------------------+-----------------------------------------------------+------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;+-----------------------------------------+-----------------------------------------------------+------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+; 2.580 ns ; 10.000 ns ; 7.420 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; CLK ;; 2.743 ns ; 10.000 ns ; 7.257 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff ; CLK ;; 2.878 ns ; 10.000 ns ; 7.122 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; CLK ;; 3.167 ns ; 10.000 ns ; 6.833 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_2_dff ; CLK ;; 3.196 ns ; 10.000 ns ; 6.804 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff ; CLK ;; 3.376 ns ; 10.000 ns ; 6.624 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; CLK ;; 3.379 ns ; 10.000 ns ; 6.621 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; CLK ;; 3.384 ns ; 10.000 ns ; 6.616 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; CLK ;; 3.439 ns ; 10.000 ns ; 6.561 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; CLK ;; 3.456 ns ; 10.000 ns ; 6.544 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; CLK ;; 3.457 ns ; 10.000 ns ; 6.543 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_0_dff ; CLK ;; 3.466 ns ; 10.000 ns ; 6.534 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_1_dff ; CLK ;; 3.527 ns ; 10.000 ns ; 6.473 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ;; 3.598 ns ; 10.000 ns ; 6.402 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ;; 3.620 ns ; 10.000 ns ; 6.380 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_2_dff ; CLK ;; 3.643 ns ; 10.000 ns ; 6.357 ns ; RD ; uart_16750:inst|iMSR_dDSR ; CLK ;; 3.651 ns ; 10.000 ns ; 6.349 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ;; 3.651 ns ; 10.000 ns ; 6.349 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ;; 3.651 ns ; 10.000 ns ; 6.349 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ;; 3.670 ns ; 10.000 ns ; 6.330 ns ; RD ; uart_16750:inst|iLSR_PE ; CLK ;; 3.671 ns ; 10.000 ns ; 6.329 ns ; RD ; uart_16750:inst|iLSR_BI ; CLK ;; 3.674 ns ; 10.000 ns ; 6.326 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; CLK ;; 3.682 ns ; 10.000 ns ; 6.318 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; CLK ;; 3.725 ns ; 10.000 ns ; 6.275 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; CLK ;; 3.737 ns ; 10.000 ns ; 6.263 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; CLK ;; 3.738 ns ; 10.000 ns ; 6.262 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; CLK ;; 3.746 ns ; 10.000 ns ; 6.254 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; CLK ;; 3.754 ns ; 10.000 ns ; 6.246 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; CLK ;; 3.768 ns ; 10.000 ns ; 6.232 ns ; RD ; uart_16750:inst|iTHRInterrupt ; CLK ;; 3.775 ns ; 10.000 ns ; 6.225 ns ; RD ; uart_16750:inst|iMSR_dDCD ; CLK ;; 3.777 ns ; 10.000 ns ; 6.223 ns ; RD ; uart_16750:inst|iMSR_TERI ; CLK ;; 3.788 ns ; 10.000 ns ; 6.212 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ;; 3.788 ns ; 10.000 ns ; 6.212 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; CLK ;; 3.788 ns ; 10.000 ns ; 6.212 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ;; 3.788 ns ; 10.000 ns ; 6.212 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ;; 3.788 ns ; 10.000 ns ; 6.212 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ;; 3.788 ns ; 10.000 ns ; 6.212 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ;; 3.825 ns ; 10.000 ns ; 6.175 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ;; 3.832 ns ; 10.000 ns ; 6.168 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; CLK ;; 3.881 ns ; 10.000 ns ; 6.119 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|full_dff ; CLK ;; 3.882 ns ; 10.000 ns ; 6.118 ns ; RD ; uart_16750:inst|iLSR_OE ; CLK ;; 3.885 ns ; 10.000 ns ; 6.115 ns ; RD ; uart_16750:inst|iLSR_FE ; CLK ;; 3.890 ns ; 10.000 ns ; 6.110 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|rd_ptr_lsb ; CLK ;; 3.896 ns ; 10.000 ns ; 6.104 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ;; 3.910 ns ; 10.000 ns ; 6.090 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_0_dff ; CLK ;; 3.919 ns ; 10.000 ns ; 6.081 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_1_dff ; CLK ;; 3.920 ns ; 10.000 ns ; 6.080 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; CLK ;; 3.920 ns ; 10.000 ns ; 6.080 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[3] ; CLK ;; 3.920 ns ; 10.000 ns ; 6.080 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[2] ; CLK ;; 3.920 ns ; 10.000 ns ; 6.080 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[1] ; CLK ;; 3.920 ns ; 10.000 ns ; 6.080 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; CLK ;; 3.933 ns ; 10.000 ns ; 6.067 ns ; RD ; uart_16750:inst|iTimeoutCount[0] ; CLK ;; 3.933 ns ; 10.000 ns ; 6.067 ns ; RD ; uart_16750:inst|iTimeoutCount[1] ; CLK ;; 3.933 ns ; 10.000 ns ; 6.067 ns ; RD ; uart_16750:inst|iTimeoutCount[2] ; CLK ;; 3.933 ns ; 10.000 ns ; 6.067 ns ; RD ; uart_16750:inst|iTimeoutCount[3] ; CLK ;; 3.933 ns ; 10.000 ns ; 6.067 ns ; RD ; uart_16750:inst|iTimeoutCount[4] ; CLK ;; 3.933 ns ; 10.000 ns ; 6.067 ns ; RD ; uart_16750:inst|iTimeoutCount[5] ; CLK ;; 3.949 ns ; 10.000 ns ; 6.051 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ;; 3.949 ns ; 10.000 ns ; 6.051 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ;; 3.949 ns ; 10.000 ns ; 6.051 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ;; 3.953 ns ; 10.000 ns ; 6.047 ns ; RD ; uart_16750:inst|iMSR_dCTS ; CLK ;; 3.995 ns ; 10.000 ns ; 6.005 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; CLK ;; 4.008 ns ; 10.000 ns ; 5.992 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; CLK ;; 4.028 ns ; 10.000 ns ; 5.972 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[2] ; CLK ;; 4.035 ns ; 10.000 ns ; 5.965 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; CLK ;; 4.039 ns ; 10.000 ns ; 5.961 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[5] ; CLK ;; 4.039 ns ; 10.000 ns ; 5.961 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; CLK ;; 4.039 ns ; 10.000 ns ; 5.961 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[3] ; CLK ;; 4.039 ns ; 10.000 ns ; 5.961 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[2] ; CLK ;; 4.039 ns ; 10.000 ns ; 5.961 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; CLK ;; 4.039 ns ; 10.000 ns ; 5.961 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[0] ; CLK ;; 4.096 ns ; 10.000 ns ; 5.904 ns ; CS ; uart_16750:inst|iMSR_dDSR ; CLK ;; 4.117 ns ; 10.000 ns ; 5.883 ns ; WR ; uart_16750:inst|iTHRInterrupt ; CLK ;; 4.131 ns ; 10.000 ns ; 5.869 ns ; WR ; uart_16750:inst|iLCR[2] ; CLK ;; 4.131 ns ; 10.000 ns ; 5.869 ns ; WR ; uart_16750:inst|iLCR[6] ; CLK ;; 4.131 ns ; 10.000 ns ; 5.869 ns ; WR ; uart_16750:inst|iLCR[1] ; CLK ;; 4.131 ns ; 10.000 ns ; 5.869 ns ; WR ; uart_16750:inst|iLCR[4] ; CLK ;; 4.141 ns ; 10.000 ns ; 5.859 ns ; WR ; uart_16750:inst|iLCR[0] ; CLK ;; 4.141 ns ; 10.000 ns ; 5.859 ns ; WR ; uart_16750:inst|iLCR[3] ; CLK ;; 4.149 ns ; 10.000 ns ; 5.851 ns ; WR ; uart_16750:inst|iDLM[3] ; CLK ;; 4.178 ns ; 10.000 ns ; 5.822 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; CLK ;; 4.179 ns ; 10.000 ns ; 5.821 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|full_dff ; CLK ;; 4.187 ns ; 10.000 ns ; 5.813 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[4] ; CLK ;; 4.187 ns ; 10.000 ns ; 5.813 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[3] ; CLK ;; 4.188 ns ; 10.000 ns ; 5.812 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[1] ; CLK ;; 4.188 ns ; 10.000 ns ; 5.812 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[0] ; CLK ;; 4.189 ns ; 10.000 ns ; 5.811 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[5] ; CLK ;; 4.191 ns ; 10.000 ns ; 5.809 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; CLK ;; 4.199 ns ; 10.000 ns ; 5.801 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; CLK ;; 4.206 ns ; 10.000 ns ; 5.794 ns ; WR ; uart_16750:inst|iDLM[2] ; CLK ;; 4.206 ns ; 10.000 ns ; 5.794 ns ; WR ; uart_16750:inst|iDLM[0] ; CLK ;; 4.206 ns ; 10.000 ns ; 5.794 ns ; WR ; uart_16750:inst|iDLM[1] ; CLK ;; 4.221 ns ; 10.000 ns ; 5.779 ns ; CS ; uart_16750:inst|iTHRInterrupt ; CLK ;; 4.228 ns ; 10.000 ns ; 5.772 ns ; CS ; uart_16750:inst|iMSR_dDCD ; CLK ;; 4.230 ns ; 10.000 ns ; 5.770 ns ; CS ; uart_16750:inst|iMSR_TERI ; CLK ;; 4.241 ns ; 10.000 ns ; 5.759 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ;; 4.241 ns ; 10.000 ns ; 5.759 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; CLK ;; 4.241 ns ; 10.000 ns ; 5.759 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ;; 4.241 ns ; 10.000 ns ; 5.759 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ;; 4.241 ns ; 10.000 ns ; 5.759 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ;; 4.241 ns ; 10.000 ns ; 5.759 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ;; 4.269 ns ; 10.000 ns ; 5.731 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|ram_block1a0~porta_we_reg ; CLK ;; 4.337 ns ; 10.000 ns ; 5.663 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[5] ; CLK ;; 4.337 ns ; 10.000 ns ; 5.663 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; CLK ;; 4.337 ns ; 10.000 ns ; 5.663 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[3] ; CLK ;; 4.337 ns ; 10.000 ns ; 5.663 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[2] ; CLK ;; 4.337 ns ; 10.000 ns ; 5.663 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; CLK ;; 4.337 ns ; 10.000 ns ; 5.663 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[0] ; CLK ;; 4.343 ns ; 10.000 ns ; 5.657 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|rd_ptr_lsb ; CLK ;; 4.373 ns ; 10.000 ns ; 5.627 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; CLK ;; 4.373 ns ; 10.000 ns ; 5.627 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[3] ; CLK ;; 4.373 ns ; 10.000 ns ; 5.627 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[2] ; CLK ;; 4.373 ns ; 10.000 ns ; 5.627 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[1] ; CLK ;; 4.373 ns ; 10.000 ns ; 5.627 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; CLK ;; 4.382 ns ; 10.000 ns ; 5.618 ns ; WR ; uart_16750:inst|iIER[3] ; CLK ;; 4.386 ns ; 10.000 ns ; 5.614 ns ; CS ; uart_16750:inst|iTimeoutCount[0] ; CLK ;; 4.386 ns ; 10.000 ns ; 5.614 ns ; CS ; uart_16750:inst|iTimeoutCount[1] ; CLK ;; 4.386 ns ; 10.000 ns ; 5.614 ns ; CS ; uart_16750:inst|iTimeoutCount[2] ; CLK ;; 4.386 ns ; 10.000 ns ; 5.614 ns ; CS ; uart_16750:inst|iTimeoutCount[3] ; CLK ;; 4.386 ns ; 10.000 ns ; 5.614 ns ; CS ; uart_16750:inst|iTimeoutCount[4] ; CLK ;; 4.386 ns ; 10.000 ns ; 5.614 ns ; CS ; uart_16750:inst|iTimeoutCount[5] ; CLK ;; 4.387 ns ; 10.000 ns ; 5.613 ns ; WR ; uart_16750:inst|iFCR_RXTrigger[1] ; CLK ;; 4.387 ns ; 10.000 ns ; 5.613 ns ; WR ; uart_16750:inst|iFCR_RXTrigger[0] ; CLK ;; 4.387 ns ; 10.000 ns ; 5.613 ns ; WR ; uart_16750:inst|iFCR_FIFOEnable ; CLK ;; 4.406 ns ; 10.000 ns ; 5.594 ns ; CS ; uart_16750:inst|iMSR_dCTS ; CLK ;; 4.408 ns ; 10.000 ns ; 5.592 ns ; WR ; uart_16750:inst|iIER[2] ; CLK ;; 4.408 ns ; 10.000 ns ; 5.592 ns ; WR ; uart_16750:inst|iIER[1] ; CLK ;; 4.408 ns ; 10.000 ns ; 5.592 ns ; WR ; uart_16750:inst|iIER[0] ; CLK ;; 4.409 ns ; 10.000 ns ; 5.591 ns ; WR ; uart_16750:inst|iDLM[7] ; CLK ;; 4.409 ns ; 10.000 ns ; 5.591 ns ; WR ; uart_16750:inst|iDLM[4] ; CLK ;; 4.409 ns ; 10.000 ns ; 5.591 ns ; WR ; uart_16750:inst|iDLM[6] ; CLK ;; 4.409 ns ; 10.000 ns ; 5.591 ns ; WR ; uart_16750:inst|iDLM[5] ; CLK ;; 4.426 ns ; 10.000 ns ; 5.574 ns ; RD ; uart_16750:inst|iCharTimeout ; CLK ;; 4.429 ns ; 10.000 ns ; 5.571 ns ; CS ; uart_16750:inst|iLCR[2] ; CLK ;; 4.429 ns ; 10.000 ns ; 5.571 ns ; CS ; uart_16750:inst|iLCR[6] ; CLK ;; 4.429 ns ; 10.000 ns ; 5.571 ns ; CS ; uart_16750:inst|iLCR[1] ; CLK ;; 4.429 ns ; 10.000 ns ; 5.571 ns ; CS ; uart_16750:inst|iLCR[4] ; CLK ;; 4.439 ns ; 10.000 ns ; 5.561 ns ; CS ; uart_16750:inst|iLCR[0] ; CLK ;; 4.439 ns ; 10.000 ns ; 5.561 ns ; CS ; uart_16750:inst|iLCR[3] ; CLK ;; 4.445 ns ; 10.000 ns ; 5.555 ns ; CS ; uart_16750:inst|iSCR[1] ; CLK ;; 4.445 ns ; 10.000 ns ; 5.555 ns ; CS ; uart_16750:inst|iSCR[2] ; CLK ;; 4.445 ns ; 10.000 ns ; 5.555 ns ; CS ; uart_16750:inst|iSCR[3] ; CLK ;; 4.447 ns ; 10.000 ns ; 5.553 ns ; CS ; uart_16750:inst|iDLM[3] ; CLK ;; 4.448 ns ; 10.000 ns ; 5.552 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; CLK ;; 4.461 ns ; 10.000 ns ; 5.539 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; CLK ;; 4.481 ns ; 10.000 ns ; 5.519 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[2] ; CLK ;; 4.488 ns ; 10.000 ns ; 5.512 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; CLK ;; 4.504 ns ; 10.000 ns ; 5.496 ns ; CS ; uart_16750:inst|iDLM[2] ; CLK ;; 4.504 ns ; 10.000 ns ; 5.496 ns ; CS ; uart_16750:inst|iDLM[0] ; CLK ;; 4.504 ns ; 10.000 ns ; 5.496 ns ; CS ; uart_16750:inst|iDLM[1] ; CLK ;; 4.518 ns ; 10.000 ns ; 5.482 ns ; WR ; uart_16750:inst|iFCR_FIFO64E ; CLK ;; 4.561 ns ; 10.000 ns ; 5.439 ns ; WR ; uart_16750:inst|iSCR[1] ; CLK ;; 4.561 ns ; 10.000 ns ; 5.439 ns ; WR ; uart_16750:inst|iSCR[2] ; CLK ;; 4.561 ns ; 10.000 ns ; 5.439 ns ; WR ; uart_16750:inst|iSCR[3] ; CLK ;; 4.567 ns ; 10.000 ns ; 5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|ram_block1a0~porta_we_reg ; CLK ;; 4.640 ns ; 10.000 ns ; 5.360 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[4] ; CLK ;; 4.640 ns ; 10.000 ns ; 5.360 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[3] ; CLK ;; 4.641 ns ; 10.000 ns ; 5.359 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[1] ; CLK ;; 4.641 ns ; 10.000 ns ; 5.359 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[0] ; CLK ;; 4.642 ns ; 10.000 ns ; 5.358 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[5] ; CLK ;; 4.680 ns ; 10.000 ns ; 5.320 ns ; CS ; uart_16750:inst|iIER[3] ; CLK ;; 4.685 ns ; 10.000 ns ; 5.315 ns ; CS ; uart_16750:inst|iFCR_RXTrigger[1] ; CLK ;; 4.685 ns ; 10.000 ns ; 5.315 ns ; CS ; uart_16750:inst|iFCR_RXTrigger[0] ; CLK ;; 4.685 ns ; 10.000 ns ; 5.315 ns ; CS ; uart_16750:inst|iFCR_FIFOEnable ; CLK ;; 4.705 ns ; 10.000 ns ; 5.295 ns ; CS ; uart_16750:inst|iLSR_PE ; CLK ;; 4.706 ns ; 10.000 ns ; 5.294 ns ; CS ; uart_16750:inst|iLSR_BI ; CLK ;; 4.706 ns ; 10.000 ns ; 5.294 ns ; CS ; uart_16750:inst|iIER[2] ; CLK ;; 4.706 ns ; 10.000 ns ; 5.294 ns ; CS ; uart_16750:inst|iIER[1] ; CLK ;; 4.706 ns ; 10.000 ns ; 5.294 ns ; CS ; uart_16750:inst|iIER[0] ; CLK ;; 4.707 ns ; 10.000 ns ; 5.293 ns ; CS ; uart_16750:inst|iDLM[7] ; CLK ;; 4.707 ns ; 10.000 ns ; 5.293 ns ; CS ; uart_16750:inst|iDLM[4] ; CLK ;; 4.707 ns ; 10.000 ns ; 5.293 ns ; CS ; uart_16750:inst|iDLM[6] ; CLK ;; 4.707 ns ; 10.000 ns ; 5.293 ns ; CS ; uart_16750:inst|iDLM[5] ; CLK ;; 4.733 ns ; 10.000 ns ; 5.267 ns ; CS ; uart_16750:inst|iSCR[0] ; CLK ;; 4.736 ns ; 10.000 ns ; 5.264 ns ; CS ; uart_16750:inst|iMCR[0] ; CLK ;; 4.736 ns ; 10.000 ns ; 5.264 ns ; CS ; uart_16750:inst|iMCR[5] ; CLK ;; 4.736 ns ; 10.000 ns ; 5.264 ns ; CS ; uart_16750:inst|iMCR[4] ; CLK ;; 4.814 ns ; 10.000 ns ; 5.186 ns ; WR ; uart_16750:inst|iFCR_RXFIFOReset ; CLK ;; 4.816 ns ; 10.000 ns ; 5.184 ns ; CS ; uart_16750:inst|iFCR_FIFO64E ; CLK ;; 4.817 ns ; 10.000 ns ; 5.183 ns ; WR ; uart_16750:inst|iFCR_TXFIFOReset ; CLK ;; 4.849 ns ; 10.000 ns ; 5.151 ns ; WR ; uart_16750:inst|iSCR[0] ; CLK ;; 4.852 ns ; 10.000 ns ; 5.148 ns ; WR ; uart_16750:inst|iMCR[0] ; CLK ;; 4.852 ns ; 10.000 ns ; 5.148 ns ; WR ; uart_16750:inst|iMCR[5] ; CLK ;; 4.852 ns ; 10.000 ns ; 5.148 ns ; WR ; uart_16750:inst|iMCR[4] ; CLK ;; 4.871 ns ; 10.000 ns ; 5.129 ns ; WR ; uart_16750:inst|iDLL[6] ; CLK ;; 4.871 ns ; 10.000 ns ; 5.129 ns ; WR ; uart_16750:inst|iDLL[7] ; CLK ;; 4.874 ns ; 10.000 ns ; 5.126 ns ; WR ; uart_16750:inst|iDLL[3] ; CLK ;; 4.874 ns ; 10.000 ns ; 5.126 ns ; WR ; uart_16750:inst|iDLL[4] ; CLK ;; 4.874 ns ; 10.000 ns ; 5.126 ns ; WR ; uart_16750:inst|iDLL[1] ; CLK ;; 4.874 ns ; 10.000 ns ; 5.126 ns ; WR ; uart_16750:inst|iDLL[2] ; CLK ;; 4.874 ns ; 10.000 ns ; 5.126 ns ; WR ; uart_16750:inst|iDLL[0] ; CLK ;; 4.879 ns ; 10.000 ns ; 5.121 ns ; CS ; uart_16750:inst|iCharTimeout ; CLK ;; 4.897 ns ; 10.000 ns ; 5.103 ns ; WR ; uart_16750:inst|iLCR[5] ; CLK ;; 4.897 ns ; 10.000 ns ; 5.103 ns ; WR ; uart_16750:inst|iLCR[7] ; CLK ;; 4.917 ns ; 10.000 ns ; 5.083 ns ; CS ; uart_16750:inst|iLSR_OE ; CLK ;; 4.920 ns ; 10.000 ns ; 5.080 ns ; CS ; uart_16750:inst|iLSR_FE ; CLK ;; 4.933 ns ; 10.000 ns ; 5.067 ns ; CS ; uart_16750:inst|iMCR[3] ; CLK ;; 4.933 ns ; 10.000 ns ; 5.067 ns ; CS ; uart_16750:inst|iMCR[2] ; CLK ;; 4.933 ns ; 10.000 ns ; 5.067 ns ; CS ; uart_16750:inst|iMCR[1] ; CLK ;; 4.964 ns ; 10.000 ns ; 5.036 ns ; CS ; uart_16750:inst|iSCR[4] ; CLK ;; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ;+-----------------------------------------+-----------------------------------------------------+------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; tco ;+----------+--------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+------------+; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;+----------+--------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+------------+; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[3] ; CLK ;; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[3] ; CLK ;; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[3] ; CLK ;; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[3] ; CLK ;; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[3] ; CLK ;; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[3] ; CLK ;; 3.224 ns ; 15.000 ns ; 11.776 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[5] ; CLK ;; 3.224 ns ; 15.000 ns ; 11.776 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[5] ; CLK ;; 3.224 ns ; 15.000 ns ; 11.776 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[5] ; CLK ;; 3.224 ns ; 15.000 ns ; 11.776 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[5] ; CLK ;; 3.224 ns ; 15.000 ns ; 11.776 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[5] ; CLK ;; 3.224 ns ; 15.000 ns ; 11.776 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[5] ; CLK ;; 3.265 ns ; 15.000 ns ; 11.735 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[0] ; CLK ;; 3.265 ns ; 15.000 ns ; 11.735 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[0] ; CLK ;; 3.265 ns ; 15.000 ns ; 11.735 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[0] ; CLK ;; 3.265 ns ; 15.000 ns ; 11.735 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[0] ; CLK ;; 3.265 ns ; 15.000 ns ; 11.735 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[0] ; CLK ;; 3.265 ns ; 15.000 ns ; 11.735 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[0] ; CLK ;; 3.443 ns ; 15.000 ns ; 11.557 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[7] ; CLK ;; 3.443 ns ; 15.000 ns ; 11.557 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[7] ; CLK ;; 3.443 ns ; 15.000 ns ; 11.557 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[7] ; CLK ;; 3.443 ns ; 15.000 ns ; 11.557 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[7] ; CLK ;; 3.443 ns ; 15.000 ns ; 11.557 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[7] ; CLK ;; 3.443 ns ; 15.000 ns ; 11.557 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[7] ; CLK ;; 3.447 ns ; 15.000 ns ; 11.553 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[2] ; CLK ;; 3.447 ns ; 15.000 ns ; 11.553 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[2] ; CLK ;; 3.447 ns ; 15.000 ns ; 11.553 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[2] ; CLK ;; 3.447 ns ; 15.000 ns ; 11.553 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[2] ; CLK ;; 3.447 ns ; 15.000 ns ; 11.553 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[2] ; CLK ;; 3.447 ns ; 15.000 ns ; 11.553 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[2] ; CLK ;; 3.639 ns ; 15.000 ns ; 11.361 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[1] ; CLK ;; 3.639 ns ; 15.000 ns ; 11.361 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[1] ; CLK ;; 3.639 ns ; 15.000 ns ; 11.361 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[1] ; CLK ;; 3.639 ns ; 15.000 ns ; 11.361 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[1] ; CLK ;; 3.639 ns ; 15.000 ns ; 11.361 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[1] ; CLK ;; 3.639 ns ; 15.000 ns ; 11.361 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[1] ; CLK ;; 3.800 ns ; 15.000 ns ; 11.200 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[4] ; CLK ;; 3.800 ns ; 15.000 ns ; 11.200 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[4] ; CLK ;; 3.800 ns ; 15.000 ns ; 11.200 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[4] ; CLK ;; 3.800 ns ; 15.000 ns ; 11.200 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[4] ; CLK ;; 3.800 ns ; 15.000 ns ; 11.200 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[4] ; CLK ;; 3.800 ns ; 15.000 ns ; 11.200 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[4] ; CLK ;; 3.944 ns ; 15.000 ns ; 11.056 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[6] ; CLK ;; 3.944 ns ; 15.000 ns ; 11.056 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[6] ; CLK ;; 3.944 ns ; 15.000 ns ; 11.056 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[6] ; CLK ;; 3.944 ns ; 15.000 ns ; 11.056 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[6] ; CLK ;; 3.944 ns ; 15.000 ns ; 11.056 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[6] ; CLK ;; 3.944 ns ; 15.000 ns ; 11.056 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[6] ; CLK ;; 4.127 ns ; 15.000 ns ; 10.873 ns ; uart_16750:inst|iLCR[7] ; DOUT[3] ; CLK ;; 4.486 ns ; 15.000 ns ; 10.514 ns ; uart_16750:inst|iLCR[7] ; DOUT[0] ; CLK ;; 4.550 ns ; 15.000 ns ; 10.450 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; DOUT[6] ; CLK ;; 4.594 ns ; 15.000 ns ; 10.406 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff ; DOUT[0] ; CLK ;; 4.722 ns ; 15.000 ns ; 10.278 ns ; uart_16750:inst|iLCR[7] ; DOUT[2] ; CLK ;; 4.875 ns ; 15.000 ns ; 10.125 ns ; uart_16750:inst|iLSR_FE ; DOUT[3] ; CLK ;; 4.894 ns ; 15.000 ns ; 10.106 ns ; uart_16750:inst|iRXFIFOWrite ; DOUT[0] ; CLK ;; 4.913 ns ; 15.000 ns ; 10.087 ns ; uart_16750:inst|iLCR[7] ; DOUT[1] ; CLK ;; 5.035 ns ; 15.000 ns ; 9.965 ns ; uart_16750:inst|iLCR[7] ; DOUT[6] ; CLK ;; 5.047 ns ; 15.000 ns ; 9.953 ns ; uart_16750:inst|iFCR_FIFOEnable ; DOUT[5] ; CLK ;; 5.084 ns ; 15.000 ns ; 9.916 ns ; uart_16750:inst|iLCR[7] ; DOUT[7] ; CLK ;; 5.114 ns ; 15.000 ns ; 9.886 ns ; uart_16750:inst|iMCR[4] ; DOUT[7] ; CLK ;; 5.228 ns ; 15.000 ns ; 9.772 ns ; uart_16750:inst|iLCR[0] ; DOUT[0] ; CLK ;; 5.254 ns ; 15.000 ns ; 9.746 ns ; uart_16750:inst|iTXRunning ; DOUT[6] ; CLK ;; 5.255 ns ; 15.000 ns ; 9.745 ns ; uart_16750:inst|iMCR[3] ; DOUT[7] ; CLK ;; 5.260 ns ; 15.000 ns ; 9.740 ns ; uart_16750:inst|iMCR[4] ; DOUT[5] ; CLK ;; 5.275 ns ; 15.000 ns ; 9.725 ns ; uart_16750:inst|iFCR_FIFO64E ; DOUT[5] ; CLK ;; 5.295 ns ; 15.000 ns ; 9.705 ns ; uart_16750:inst|iLSR_FIFOERR ; DOUT[7] ; CLK ;; 5.307 ns ; 15.000 ns ; 9.693 ns ; uart_16750:inst|iLCR[7] ; DOUT[5] ; CLK ;; 5.413 ns ; 15.000 ns ; 9.587 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|Q ; DOUT[5] ; CLK ;; 5.487 ns ; 15.000 ns ; 9.513 ns ; uart_16750:inst|iDLM[3] ; DOUT[3] ; CLK ;; 5.503 ns ; 15.000 ns ; 9.497 ns ; uart_16750:inst|iIER[3] ; DOUT[3] ; CLK ;; 5.549 ns ; 15.000 ns ; 9.451 ns ; uart_16750:inst|iMCR[4] ; DOUT[6] ; CLK ;; 5.571 ns ; 15.000 ns ; 9.429 ns ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[3] ; DOUT[3] ; CLK ;; 5.612 ns ; 15.000 ns ; 9.388 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|Q ; DOUT[7] ; CLK ;; 5.711 ns ; 15.000 ns ; 9.289 ns ; uart_16750:inst|iDLM[4] ; DOUT[4] ; CLK ;; 5.737 ns ; 15.000 ns ; 9.263 ns ; uart_16750:inst|iMCR[0] ; DOUT[5] ; CLK ;; 5.798 ns ; 15.000 ns ; 9.202 ns ; uart_16750:inst|iMCR[2] ; DOUT[6] ; CLK ;; 5.841 ns ; 15.000 ns ; 9.159 ns ; uart_16750:inst|iLSR_OE ; DOUT[1] ; CLK ;; 5.899 ns ; 15.000 ns ; 9.101 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|Q ; DOUT[6] ; CLK ;; 5.936 ns ; 15.000 ns ; 9.064 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|Q ; DOUT[4] ; CLK ;; 5.950 ns ; 15.000 ns ; 9.050 ns ; uart_16750:inst|iDLM[5] ; DOUT[5] ; CLK ;; 5.956 ns ; 15.000 ns ; 9.044 ns ; uart_16750:inst|iDLM[0] ; DOUT[0] ; CLK ;; 6.113 ns ; 15.000 ns ; 8.887 ns ; uart_16750:inst|iRTS ; DOUT[4] ; CLK ;; 6.114 ns ; 15.000 ns ; 8.886 ns ; uart_16750:inst|iLCR[7] ; DOUT[4] ; CLK ;; 6.123 ns ; 15.000 ns ; 8.877 ns ; uart_16750:inst|iLSR_BI ; DOUT[4] ; CLK ;; 6.142 ns ; 15.000 ns ; 8.858 ns ; uart_16750:inst|iDLL[3] ; DOUT[3] ; CLK ;; 6.145 ns ; 15.000 ns ; 8.855 ns ; uart_16750:inst|iLCR[2] ; DOUT[2] ; CLK ;; 6.157 ns ; 15.000 ns ; 8.843 ns ; uart_16750:inst|iMCR[5] ; DOUT[5] ; CLK ;; 6.185 ns ; 15.000 ns ; 8.815 ns ; uart_16750:inst|iFCR_FIFOEnable ; DOUT[7] ; CLK ;; 6.218 ns ; 15.000 ns ; 8.782 ns ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; DOUT[0] ; CLK ;; 6.240 ns ; 15.000 ns ; 8.760 ns ; uart_16750:inst|iMCR[0] ; DOUT[0] ; CLK ;; 6.256 ns ; 15.000 ns ; 8.744 ns ; uart_16750:inst|iMCR[4] ; DOUT[4] ; CLK ;; 6.266 ns ; 15.000 ns ; 8.734 ns ; uart_16750:inst|iFCR_FIFOEnable ; DOUT[6] ; CLK ;; 6.278 ns ; 15.000 ns ; 8.722 ns ; uart_16750:inst|iLCR[1] ; DOUT[1] ; CLK ;; 6.287 ns ; 15.000 ns ; 8.713 ns ; uart_16750:inst|iLSR_PE ; DOUT[2] ; CLK ;; 6.326 ns ; 15.000 ns ; 8.674 ns ; uart_16750:inst|iDLL[4] ; DOUT[4] ; CLK ;; 6.351 ns ; 15.000 ns ; 8.649 ns ; uart_16750:inst|iIER[0] ; DOUT[0] ; CLK ;; 6.353 ns ; 15.000 ns ; 8.647 ns ; uart_16750:inst|iDLM[6] ; DOUT[6] ; CLK ;; 6.386 ns ; 15.000 ns ; 8.614 ns ; uart_16750:inst|iLCR[3] ; DOUT[3] ; CLK ;; 6.400 ns ; 15.000 ns ; 8.600 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; DOUT[5] ; CLK ;; 6.408 ns ; 15.000 ns ; 8.592 ns ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[2] ; DOUT[2] ; CLK ;; 6.528 ns ; 15.000 ns ; 8.472 ns ; uart_16750:inst|iLCR[6] ; DOUT[6] ; CLK ;; 6.571 ns ; 15.000 ns ; 8.429 ns ; uart_16750:inst|iDLL[0] ; DOUT[0] ; CLK ;; 6.575 ns ; 15.000 ns ; 8.425 ns ; uart_16750:inst|iDLM[7] ; DOUT[7] ; CLK ;; 6.580 ns ; 15.000 ns ; 8.420 ns ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[1] ; DOUT[1] ; CLK ;; 6.607 ns ; 15.000 ns ; 8.393 ns ; uart_16750:inst|iDLM[2] ; DOUT[2] ; CLK ;; 6.723 ns ; 15.000 ns ; 8.277 ns ; uart_16750:inst|iDLM[1] ; DOUT[1] ; CLK ;; 6.731 ns ; 15.000 ns ; 8.269 ns ; uart_16750:inst|iMCR[3] ; DOUT[3] ; CLK ;; 6.732 ns ; 15.000 ns ; 8.268 ns ; uart_16750:inst|iDLL[2] ; DOUT[2] ; CLK ;; 6.780 ns ; 15.000 ns ; 8.220 ns ; uart_16750:inst|iMSR_dDCD ; DOUT[3] ; CLK ;; 6.806 ns ; 15.000 ns ; 8.194 ns ; uart_16750:inst|iDLL[5] ; DOUT[5] ; CLK ;; 6.885 ns ; 15.000 ns ; 8.115 ns ; uart_16750:inst|iDLL[6] ; DOUT[6] ; CLK ;; 6.924 ns ; 15.000 ns ; 8.076 ns ; uart_16750:inst|iDLL[1] ; DOUT[1] ; CLK ;; 6.927 ns ; 15.000 ns ; 8.073 ns ; uart_16750:inst|iDLL[7] ; DOUT[7] ; CLK ;; 6.998 ns ; 15.000 ns ; 8.002 ns ; uart_16750:inst|iIER[2] ; DOUT[2] ; CLK ;; 7.115 ns ; 15.000 ns ; 7.885 ns ; uart_16750:inst|iIER[1] ; DOUT[1] ; CLK ;; 7.262 ns ; 15.000 ns ; 7.738 ns ; uart_16750:inst|iSCR[5] ; DOUT[5] ; CLK ;; 7.263 ns ; 15.000 ns ; 7.737 ns ; uart_16750:inst|iMSR_TERI ; DOUT[2] ; CLK ;; 7.317 ns ; 15.000 ns ; 7.683 ns ; uart_16750:inst|iMSR_dCTS ; DOUT[0] ; CLK ;; 7.319 ns ; 15.000 ns ; 7.681 ns ; uart_16750:inst|iMCR[2] ; DOUT[2] ; CLK ;; 7.390 ns ; 15.000 ns ; 7.610 ns ; uart_16750:inst|iSCR[4] ; DOUT[4] ; CLK ;; 7.451 ns ; 15.000 ns ; 7.549 ns ; uart_16750:inst|iSCR[7] ; DOUT[7] ; CLK ;; 7.462 ns ; 15.000 ns ; 7.538 ns ; uart_16750:inst|iMCR[1] ; DOUT[1] ; CLK ;; 7.474 ns ; 15.000 ns ; 7.526 ns ; uart_16750:inst|iMSR_dDSR ; DOUT[1] ; CLK ;; 7.600 ns ; 15.000 ns ; 7.400 ns ; uart_16750:inst|iLCR[5] ; DOUT[5] ; CLK ;; 7.654 ns ; 15.000 ns ; 7.346 ns ; uart_16750:inst|iSCR[3] ; DOUT[3] ; CLK ;; 7.704 ns ; 15.000 ns ; 7.296 ns ; uart_16750:inst|iLCR[4] ; DOUT[4] ; CLK ;; 7.711 ns ; 15.000 ns ; 7.289 ns ; uart_16750:inst|iSCR[6] ; DOUT[6] ; CLK ;; 8.115 ns ; 15.000 ns ; 6.885 ns ; uart_16750:inst|iSCR[2] ; DOUT[2] ; CLK ;; 8.167 ns ; 15.000 ns ; 6.833 ns ; uart_16750:inst|iSCR[0] ; DOUT[0] ; CLK ;; 8.198 ns ; 15.000 ns ; 6.802 ns ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; INT ; CLK ;; 8.201 ns ; 15.000 ns ; 6.799 ns ; uart_16750:inst|DDIS ; DDIS ; CLK ;; 8.386 ns ; 15.000 ns ; 6.614 ns ; uart_16750:inst|iSCR[1] ; DOUT[1] ; CLK ;; 8.486 ns ; 15.000 ns ; 6.514 ns ; uart_16750:inst|RTSN ; RTSN ; CLK ;; 8.509 ns ; 15.000 ns ; 6.491 ns ; uart_16750:inst|DTRN ; DTRN ; CLK ;; 8.711 ns ; 15.000 ns ; 6.289 ns ; uart_16750:inst|SOUT ; SOUT ; CLK ;; 8.844 ns ; 15.000 ns ; 6.156 ns ; uart_16750:inst|OUT1N ; OUT1N ; CLK ;; 8.977 ns ; 15.000 ns ; 6.023 ns ; uart_16750:inst|OUT2N ; OUT2N ; CLK ;+----------+--------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+------------++--------------------------------------------------------------+; tpd ;+-------+-------------------+-----------------+------+---------+; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;+-------+-------------------+-----------------+------+---------+; N/A ; None ; 14.563 ns ; A[1] ; DOUT[3] ;; N/A ; None ; 14.343 ns ; A[2] ; DOUT[3] ;; N/A ; None ; 14.204 ns ; A[1] ; DOUT[0] ;; N/A ; None ; 13.968 ns ; A[1] ; DOUT[2] ;; N/A ; None ; 13.938 ns ; A[2] ; DOUT[0] ;; N/A ; None ; 13.777 ns ; A[1] ; DOUT[1] ;; N/A ; None ; 13.702 ns ; A[2] ; DOUT[2] ;; N/A ; None ; 13.511 ns ; A[2] ; DOUT[1] ;; N/A ; None ; 13.266 ns ; A[1] ; DOUT[6] ;; N/A ; None ; 13.217 ns ; A[1] ; DOUT[7] ;; N/A ; None ; 13.057 ns ; A[0] ; DOUT[5] ;; N/A ; None ; 12.967 ns ; A[2] ; DOUT[6] ;; N/A ; None ; 12.958 ns ; A[0] ; DOUT[4] ;; N/A ; None ; 12.797 ns ; A[1] ; DOUT[5] ;; N/A ; None ; 12.778 ns ; A[2] ; DOUT[7] ;; N/A ; None ; 12.697 ns ; A[1] ; DOUT[4] ;; N/A ; None ; 11.717 ns ; A[0] ; DOUT[3] ;; N/A ; None ; 11.264 ns ; A[0] ; DOUT[2] ;; N/A ; None ; 11.071 ns ; A[0] ; DOUT[0] ;; N/A ; None ; 10.987 ns ; A[0] ; DOUT[1] ;; N/A ; None ; 10.837 ns ; A[0] ; DOUT[7] ;; N/A ; None ; 10.686 ns ; A[2] ; DOUT[4] ;; N/A ; None ; 10.584 ns ; A[0] ; DOUT[6] ;; N/A ; None ; 10.286 ns ; A[2] ; DOUT[5] ;+-------+-------------------+-----------------+------+---------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; th ;+-----------------------------------------+-----------------------------------------------------+-----------+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;+-----------------------------------------+-----------------------------------------------------+-----------+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+; N/A ; None ; -2.602 ns ; WR ; uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd ; CLK ;; N/A ; None ; -2.855 ns ; CS ; uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd ; CLK ;; N/A ; None ; -2.879 ns ; CS ; uart_16750:inst|DDIS ; CLK ;; N/A ; None ; -2.910 ns ; RSTN ; inst4 ; CLK ;; N/A ; None ; -2.916 ns ; DCDN ; uart_16750:inst|slib_input_sync:UART_IS_DCD|iD[0] ; CLK ;; N/A ; None ; -2.920 ns ; CTSN ; uart_16750:inst|slib_input_sync:UART_IS_CTS|iD[0] ; CLK ;; N/A ; None ; -3.212 ns ; DIN[3] ; uart_16750:inst|iDIN[3] ; CLK ;; N/A ; None ; -3.215 ns ; DIN[7] ; uart_16750:inst|iDIN[7] ; CLK ;; N/A ; None ; -3.218 ns ; DIN[5] ; uart_16750:inst|iDIN[5] ; CLK ;; N/A ; None ; -3.333 ns ; DSRN ; uart_16750:inst|slib_input_sync:UART_IS_DSR|iD[0] ; CLK ;; N/A ; None ; -3.351 ns ; RIN ; uart_16750:inst|slib_input_sync:UART_IS_RI|iD[0] ; CLK ;; N/A ; None ; -3.355 ns ; DIN[6] ; uart_16750:inst|iDIN[6] ; CLK ;; N/A ; None ; -3.362 ns ; DIN[4] ; uart_16750:inst|iDIN[4] ; CLK ;; N/A ; None ; -3.410 ns ; CS ; uart_16750:inst|slib_edge_detect:UART_ED_READ|iDd ; CLK ;; N/A ; None ; -3.536 ns ; DIN[2] ; uart_16750:inst|iDIN[2] ; CLK ;; N/A ; None ; -3.599 ns ; A[0] ; uart_16750:inst|iA[0] ; CLK ;; N/A ; None ; -3.613 ns ; A[1] ; uart_16750:inst|iA[1] ; CLK ;; N/A ; None ; -3.626 ns ; DIN[0] ; uart_16750:inst|iDIN[0] ; CLK ;; N/A ; None ; -3.629 ns ; A[2] ; uart_16750:inst|iA[2] ; CLK ;; N/A ; None ; -3.914 ns ; RD ; uart_16750:inst|DDIS ; CLK ;; N/A ; None ; -4.038 ns ; SIN ; uart_16750:inst|slib_input_sync:UART_IS_SIN|iD[0] ; CLK ;; N/A ; None ; -4.040 ns ; DIN[1] ; uart_16750:inst|iDIN[1] ; CLK ;; N/A ; None ; -4.183 ns ; CS ; uart_16750:inst|iTHRInterrupt ; CLK ;; N/A ; None ; -4.323 ns ; CS ; uart_16750:inst|iDLL[5] ; CLK ;; N/A ; None ; -4.410 ns ; WR ; uart_16750:inst|iSCR[7] ; CLK ;; N/A ; None ; -4.410 ns ; WR ; uart_16750:inst|iSCR[6] ; CLK ;; N/A ; None ; -4.410 ns ; WR ; uart_16750:inst|iSCR[5] ; CLK ;; N/A ; None ; -4.445 ns ; RD ; uart_16750:inst|slib_edge_detect:UART_ED_READ|iDd ; CLK ;; N/A ; None ; -4.481 ns ; WR ; uart_16750:inst|iTHRInterrupt ; CLK ;; N/A ; None ; -4.526 ns ; CS ; uart_16750:inst|iSCR[7] ; CLK ;; N/A ; None ; -4.526 ns ; CS ; uart_16750:inst|iSCR[6] ; CLK ;; N/A ; None ; -4.526 ns ; CS ; uart_16750:inst|iSCR[5] ; CLK ;; N/A ; None ; -4.575 ns ; CS ; uart_16750:inst|iLCR[7] ; CLK ;; N/A ; None ; -4.575 ns ; CS ; uart_16750:inst|iLCR[5] ; CLK ;; N/A ; None ; -4.598 ns ; CS ; uart_16750:inst|iDLL[0] ; CLK ;; N/A ; None ; -4.598 ns ; CS ; uart_16750:inst|iDLL[2] ; CLK ;; N/A ; None ; -4.598 ns ; CS ; uart_16750:inst|iDLL[1] ; CLK ;; N/A ; None ; -4.598 ns ; CS ; uart_16750:inst|iDLL[4] ; CLK ;; N/A ; None ; -4.598 ns ; CS ; uart_16750:inst|iDLL[3] ; CLK ;; N/A ; None ; -4.601 ns ; CS ; uart_16750:inst|iDLL[7] ; CLK ;; N/A ; None ; -4.601 ns ; CS ; uart_16750:inst|iDLL[6] ; CLK ;; N/A ; None ; -4.621 ns ; WR ; uart_16750:inst|iDLL[5] ; CLK ;; N/A ; None ; -4.655 ns ; CS ; uart_16750:inst|iFCR_TXFIFOReset ; CLK ;; N/A ; None ; -4.658 ns ; CS ; uart_16750:inst|iFCR_RXFIFOReset ; CLK ;; N/A ; None ; -4.690 ns ; WR ; uart_16750:inst|iSCR[4] ; CLK ;; N/A ; None ; -4.721 ns ; WR ; uart_16750:inst|iMCR[1] ; CLK ;; N/A ; None ; -4.721 ns ; WR ; uart_16750:inst|iMCR[2] ; CLK ;; N/A ; None ; -4.721 ns ; WR ; uart_16750:inst|iMCR[3] ; CLK ;; N/A ; None ; -4.806 ns ; CS ; uart_16750:inst|iSCR[4] ; CLK ;; N/A ; None ; -4.837 ns ; CS ; uart_16750:inst|iMCR[1] ; CLK ;; N/A ; None ; -4.837 ns ; CS ; uart_16750:inst|iMCR[2] ; CLK ;; N/A ; None ; -4.837 ns ; CS ; uart_16750:inst|iMCR[3] ; CLK ;; N/A ; None ; -4.850 ns ; CS ; uart_16750:inst|iLSR_FE ; CLK ;; N/A ; None ; -4.853 ns ; CS ; uart_16750:inst|iLSR_OE ; CLK ;; N/A ; None ; -4.873 ns ; WR ; uart_16750:inst|iLCR[7] ; CLK ;; N/A ; None ; -4.873 ns ; WR ; uart_16750:inst|iLCR[5] ; CLK ;; N/A ; None ; -4.891 ns ; CS ; uart_16750:inst|iCharTimeout ; CLK ;; N/A ; None ; -4.896 ns ; WR ; uart_16750:inst|iDLL[0] ; CLK ;; N/A ; None ; -4.896 ns ; WR ; uart_16750:inst|iDLL[2] ; CLK ;; N/A ; None ; -4.896 ns ; WR ; uart_16750:inst|iDLL[1] ; CLK ;; N/A ; None ; -4.896 ns ; WR ; uart_16750:inst|iDLL[4] ; CLK ;; N/A ; None ; -4.896 ns ; WR ; uart_16750:inst|iDLL[3] ; CLK ;; N/A ; None ; -4.899 ns ; WR ; uart_16750:inst|iDLL[7] ; CLK ;; N/A ; None ; -4.899 ns ; WR ; uart_16750:inst|iDLL[6] ; CLK ;; N/A ; None ; -4.918 ns ; WR ; uart_16750:inst|iMCR[4] ; CLK ;; N/A ; None ; -4.918 ns ; WR ; uart_16750:inst|iMCR[5] ; CLK ;; N/A ; None ; -4.918 ns ; WR ; uart_16750:inst|iMCR[0] ; CLK ;; N/A ; None ; -4.921 ns ; WR ; uart_16750:inst|iSCR[0] ; CLK ;; N/A ; None ; -4.953 ns ; WR ; uart_16750:inst|iFCR_TXFIFOReset ; CLK ;; N/A ; None ; -4.954 ns ; CS ; uart_16750:inst|iFCR_FIFO64E ; CLK ;; N/A ; None ; -4.956 ns ; WR ; uart_16750:inst|iFCR_RXFIFOReset ; CLK ;; N/A ; None ; -5.034 ns ; CS ; uart_16750:inst|iMCR[4] ; CLK ;; N/A ; None ; -5.034 ns ; CS ; uart_16750:inst|iMCR[5] ; CLK ;; N/A ; None ; -5.034 ns ; CS ; uart_16750:inst|iMCR[0] ; CLK ;; N/A ; None ; -5.037 ns ; CS ; uart_16750:inst|iSCR[0] ; CLK ;; N/A ; None ; -5.053 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; CLK ;; N/A ; None ; -5.055 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; CLK ;; N/A ; None ; -5.056 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; CLK ;; N/A ; None ; -5.063 ns ; CS ; uart_16750:inst|iDLM[5] ; CLK ;; N/A ; None ; -5.063 ns ; CS ; uart_16750:inst|iDLM[6] ; CLK ;; N/A ; None ; -5.063 ns ; CS ; uart_16750:inst|iDLM[4] ; CLK ;; N/A ; None ; -5.063 ns ; CS ; uart_16750:inst|iDLM[7] ; CLK ;; N/A ; None ; -5.064 ns ; CS ; uart_16750:inst|iIER[0] ; CLK ;; N/A ; None ; -5.064 ns ; CS ; uart_16750:inst|iIER[1] ; CLK ;; N/A ; None ; -5.064 ns ; CS ; uart_16750:inst|iIER[2] ; CLK ;; N/A ; None ; -5.064 ns ; CS ; uart_16750:inst|iLSR_BI ; CLK ;; N/A ; None ; -5.065 ns ; CS ; uart_16750:inst|iLSR_PE ; CLK ;; N/A ; None ; -5.085 ns ; CS ; uart_16750:inst|iFCR_FIFOEnable ; CLK ;; N/A ; None ; -5.085 ns ; CS ; uart_16750:inst|iFCR_RXTrigger[0] ; CLK ;; N/A ; None ; -5.085 ns ; CS ; uart_16750:inst|iFCR_RXTrigger[1] ; CLK ;; N/A ; None ; -5.090 ns ; CS ; uart_16750:inst|iIER[3] ; CLK ;; N/A ; None ; -5.128 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[5] ; CLK ;; N/A ; None ; -5.129 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[0] ; CLK ;; N/A ; None ; -5.129 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[1] ; CLK ;; N/A ; None ; -5.130 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[3] ; CLK ;; N/A ; None ; -5.130 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[4] ; CLK ;; N/A ; None ; -5.135 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_1_dff ; CLK ;; N/A ; None ; -5.164 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|ram_block1a0~porta_we_reg ; CLK ;; N/A ; None ; -5.209 ns ; WR ; uart_16750:inst|iSCR[3] ; CLK ;; N/A ; None ; -5.209 ns ; WR ; uart_16750:inst|iSCR[2] ; CLK ;; N/A ; None ; -5.209 ns ; WR ; uart_16750:inst|iSCR[1] ; CLK ;; N/A ; None ; -5.243 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; CLK ;; N/A ; None ; -5.252 ns ; WR ; uart_16750:inst|iFCR_FIFO64E ; CLK ;; N/A ; None ; -5.266 ns ; CS ; uart_16750:inst|iDLM[1] ; CLK ;; N/A ; None ; -5.266 ns ; CS ; uart_16750:inst|iDLM[0] ; CLK ;; N/A ; None ; -5.266 ns ; CS ; uart_16750:inst|iDLM[2] ; CLK ;; N/A ; None ; -5.270 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; CLK ;; N/A ; None ; -5.283 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; CLK ;; N/A ; None ; -5.289 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[2] ; CLK ;; N/A ; None ; -5.323 ns ; CS ; uart_16750:inst|iDLM[3] ; CLK ;; N/A ; None ; -5.325 ns ; CS ; uart_16750:inst|iSCR[3] ; CLK ;; N/A ; None ; -5.325 ns ; CS ; uart_16750:inst|iSCR[2] ; CLK ;; N/A ; None ; -5.325 ns ; CS ; uart_16750:inst|iSCR[1] ; CLK ;; N/A ; None ; -5.331 ns ; CS ; uart_16750:inst|iLCR[3] ; CLK ;; N/A ; None ; -5.331 ns ; CS ; uart_16750:inst|iLCR[0] ; CLK ;; N/A ; None ; -5.341 ns ; CS ; uart_16750:inst|iLCR[4] ; CLK ;; N/A ; None ; -5.341 ns ; CS ; uart_16750:inst|iLCR[1] ; CLK ;; N/A ; None ; -5.341 ns ; CS ; uart_16750:inst|iLCR[6] ; CLK ;; N/A ; None ; -5.341 ns ; CS ; uart_16750:inst|iLCR[2] ; CLK ;; N/A ; None ; -5.344 ns ; RD ; uart_16750:inst|iCharTimeout ; CLK ;; N/A ; None ; -5.349 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ;; N/A ; None ; -5.350 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ;; N/A ; None ; -5.351 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; CLK ;; N/A ; None ; -5.351 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ;; N/A ; None ; -5.351 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ;; N/A ; None ; -5.352 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ;; N/A ; None ; -5.353 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; CLK ;; N/A ; None ; -5.354 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; CLK ;; N/A ; None ; -5.361 ns ; WR ; uart_16750:inst|iDLM[5] ; CLK ;; N/A ; None ; -5.361 ns ; WR ; uart_16750:inst|iDLM[6] ; CLK ;; N/A ; None ; -5.361 ns ; WR ; uart_16750:inst|iDLM[4] ; CLK ;; N/A ; None ; -5.361 ns ; WR ; uart_16750:inst|iDLM[7] ; CLK ;; N/A ; None ; -5.362 ns ; WR ; uart_16750:inst|iIER[0] ; CLK ;; N/A ; None ; -5.362 ns ; WR ; uart_16750:inst|iIER[1] ; CLK ;; N/A ; None ; -5.362 ns ; WR ; uart_16750:inst|iIER[2] ; CLK ;; N/A ; None ; -5.364 ns ; CS ; uart_16750:inst|iMSR_dCTS ; CLK ;; N/A ; None ; -5.383 ns ; WR ; uart_16750:inst|iFCR_FIFOEnable ; CLK ;; N/A ; None ; -5.383 ns ; WR ; uart_16750:inst|iFCR_RXTrigger[0] ; CLK ;; N/A ; None ; -5.383 ns ; WR ; uart_16750:inst|iFCR_RXTrigger[1] ; CLK ;; N/A ; None ; -5.384 ns ; CS ; uart_16750:inst|iTimeoutCount[5] ; CLK ;; N/A ; None ; -5.384 ns ; CS ; uart_16750:inst|iTimeoutCount[4] ; CLK ;; N/A ; None ; -5.384 ns ; CS ; uart_16750:inst|iTimeoutCount[3] ; CLK ;; N/A ; None ; -5.384 ns ; CS ; uart_16750:inst|iTimeoutCount[2] ; CLK ;; N/A ; None ; -5.384 ns ; CS ; uart_16750:inst|iTimeoutCount[1] ; CLK ;; N/A ; None ; -5.384 ns ; CS ; uart_16750:inst|iTimeoutCount[0] ; CLK ;; N/A ; None ; -5.388 ns ; WR ; uart_16750:inst|iIER[3] ; CLK ;; N/A ; None ; -5.397 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; CLK ;; N/A ; None ; -5.397 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[1] ; CLK ;; N/A ; None ; -5.397 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[2] ; CLK ;; N/A ; None ; -5.397 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[3] ; CLK ;; N/A ; None ; -5.397 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; CLK ;; N/A ; None ; -5.422 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; CLK ;; N/A ; None ; -5.427 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|rd_ptr_lsb ; CLK ;; N/A ; None ; -5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[0] ; CLK ;; N/A ; None ; -5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; CLK ;; N/A ; None ; -5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[2] ; CLK ;; N/A ; None ; -5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[3] ; CLK ;; N/A ; None ; -5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; CLK ;; N/A ; None ; -5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[5] ; CLK ;; N/A ; None ; -5.452 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_2_dff ; CLK ;; N/A ; None ; -5.462 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|ram_block1a0~porta_we_reg ; CLK ;; N/A ; None ; -5.529 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ;; N/A ; None ; -5.529 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ;; N/A ; None ; -5.529 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ;; N/A ; None ; -5.529 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ;; N/A ; None ; -5.529 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; CLK ;; N/A ; None ; -5.529 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ;; N/A ; None ; -5.532 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; CLK ;; N/A ; None ; -5.540 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; CLK ;; N/A ; None ; -5.540 ns ; CS ; uart_16750:inst|iMSR_TERI ; CLK ;; N/A ; None ; -5.542 ns ; CS ; uart_16750:inst|iMSR_dDCD ; CLK ;; N/A ; None ; -5.564 ns ; WR ; uart_16750:inst|iDLM[1] ; CLK ;; N/A ; None ; -5.564 ns ; WR ; uart_16750:inst|iDLM[0] ; CLK ;; N/A ; None ; -5.564 ns ; WR ; uart_16750:inst|iDLM[2] ; CLK ;; N/A ; None ; -5.581 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[5] ; CLK ;; N/A ; None ; -5.582 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[0] ; CLK ;; N/A ; None ; -5.582 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[1] ; CLK ;; N/A ; None ; -5.583 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[3] ; CLK ;; N/A ; None ; -5.583 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[4] ; CLK ;; N/A ; None ; -5.588 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_1_dff ; CLK ;; N/A ; None ; -5.591 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|full_dff ; CLK ;; N/A ; None ; -5.592 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; CLK ;; N/A ; None ; -5.621 ns ; WR ; uart_16750:inst|iDLM[3] ; CLK ;; N/A ; None ; -5.629 ns ; WR ; uart_16750:inst|iLCR[3] ; CLK ;; N/A ; None ; -5.629 ns ; WR ; uart_16750:inst|iLCR[0] ; CLK ;; N/A ; None ; -5.639 ns ; WR ; uart_16750:inst|iLCR[4] ; CLK ;; N/A ; None ; -5.639 ns ; WR ; uart_16750:inst|iLCR[1] ; CLK ;; N/A ; None ; -5.639 ns ; WR ; uart_16750:inst|iLCR[6] ; CLK ;; N/A ; None ; -5.639 ns ; WR ; uart_16750:inst|iLCR[2] ; CLK ;; N/A ; None ; -5.647 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ;; N/A ; None ; -5.648 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ;; N/A ; None ; -5.649 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ;; N/A ; None ; -5.649 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ;; N/A ; None ; -5.650 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ;; N/A ; None ; -5.674 ns ; CS ; uart_16750:inst|iMSR_dDSR ; CLK ;; N/A ; None ; -5.696 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; CLK ;; N/A ; None ; -5.720 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; CLK ;; N/A ; None ; -5.723 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; CLK ;; N/A ; None ; -5.731 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[0] ; CLK ;; N/A ; None ; -5.731 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; CLK ;; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ;+-----------------------------------------+-----------------------------------------------------+-----------+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------++--------------------------+; Timing Analyzer Messages ;+--------------------------+Info: *******************************************************************Info: Running Quartus II Classic Timing AnalyzerInfo: Version 8.0 Build 215 05/29/2008 SJ Full VersionInfo: Processing started: Tue Feb 17 23:02:39 2009Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off UART16750 -c UART16750 --timing_analysis_onlyInfo: Slack time is 22.036 ns for clock "CLK" between source memory "uart_16750:inst|iTSR[3]" and destination register "uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4]"Info: Fmax is 125.52 MHz (period= 7.967 ns)Info: + Largest memory to register requirement is 29.788 nsInfo: + Setup relationship between source and destination is 30.003 nsInfo: + Latch edge is 30.003 nsInfo: Clock period of Destination clock "CLK" is 30.003 ns with offset of 0.000 ns and duty cycle of 50Info: Multicycle Setup factor for Destination register is 1Info: - Launch edge is 0.000 nsInfo: Clock period of Source clock "CLK" is 30.003 ns with offset of 0.000 ns and duty cycle of 50Info: Multicycle Setup factor for Source register is 1Info: + Largest clock skew is -0.042 nsInfo: + Shortest clock path from clock "CLK" to destination register is 2.345 nsInfo: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK'Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl'Info: 3: + IC(0.710 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X18_Y4_N15; Fanout = 2; REG Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4]'Info: Total cell delay = 1.516 ns ( 64.65 % )Info: Total interconnect delay = 0.829 ns ( 35.35 % )Info: - Longest clock path from clock "CLK" to source memory is 2.387 nsInfo: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK'Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl'Info: 3: + IC(0.653 ns) + CELL(0.636 ns) = 2.387 ns; Loc. = M4K_X23_Y5; Fanout = 2; MEM Node = 'uart_16750:inst|iTSR[3]'Info: Total cell delay = 1.615 ns ( 67.66 % )Info: Total interconnect delay = 0.772 ns ( 32.34 % )Info: - Micro clock to output delay of source is 0.209 nsInfo: - Micro setup delay of destination is -0.036 nsInfo: - Longest memory to register delay is 7.752 nsInfo: 1: + IC(0.000 ns) + CELL(0.088 ns) = 0.088 ns; Loc. = M4K_X23_Y5; Fanout = 2; MEM Node = 'uart_16750:inst|iTSR[3]'Info: 2: + IC(0.953 ns) + CELL(0.438 ns) = 1.479 ns; Loc. = LCCOMB_X21_Y4_N26; Fanout = 1; COMB Node = 'uart_16750:inst|uart_transmitter:UART_TX|Selector4~277'Info: 3: + IC(0.249 ns) + CELL(0.416 ns) = 2.144 ns; Loc. = LCCOMB_X21_Y4_N14; Fanout = 1; COMB Node = 'uart_16750:inst|uart_transmitter:UART_TX|Selector4~278'Info: 4: + IC(0.708 ns) + CELL(0.420 ns) = 3.272 ns; Loc. = LCCOMB_X21_Y4_N20; Fanout = 2; COMB Node = 'uart_16750:inst|uart_transmitter:UART_TX|Selector4~281'Info: 5: + IC(0.977 ns) + CELL(0.438 ns) = 4.687 ns; Loc. = LCCOMB_X18_Y3_N6; Fanout = 1; COMB Node = 'uart_16750:inst|iSIN~127'Info: 6: + IC(0.282 ns) + CELL(0.438 ns) = 5.407 ns; Loc. = LCCOMB_X18_Y3_N18; Fanout = 4; COMB Node = 'uart_16750:inst|iSIN~128'Info: 7: + IC(0.727 ns) + CELL(0.275 ns) = 6.409 ns; Loc. = LCCOMB_X18_Y4_N2; Fanout = 2; COMB Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|MV_PROC~0'Info: 8: + IC(0.243 ns) + CELL(0.393 ns) = 7.045 ns; Loc. = LCCOMB_X18_Y4_N6; Fanout = 2; COMB Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0]~205'Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 7.116 ns; Loc. = LCCOMB_X18_Y4_N8; Fanout = 2; COMB Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1]~207'Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 7.187 ns; Loc. = LCCOMB_X18_Y4_N10; Fanout = 2; COMB Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2]~209'Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 7.258 ns; Loc. = LCCOMB_X18_Y4_N12; Fanout = 1; COMB Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3]~211'Info: 12: + IC(0.000 ns) + CELL(0.410 ns) = 7.668 ns; Loc. = LCCOMB_X18_Y4_N14; Fanout = 1; COMB Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4]~212'Info: 13: + IC(0.000 ns) + CELL(0.084 ns) = 7.752 ns; Loc. = LCFF_X18_Y4_N15; Fanout = 2; REG Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4]'Info: Total cell delay = 3.613 ns ( 46.61 % )Info: Total interconnect delay = 4.139 ns ( 53.39 % )Info: Minimum slack time is 391 ps for clock "CLK" between source register "uart_16750:inst|iLSR_FIFOERR" and destination register "uart_16750:inst|iLSR_FIFOERR"Info: + Shortest register to register delay is 0.407 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y3_N1; Fanout = 2; REG Node = 'uart_16750:inst|iLSR_FIFOERR'Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X26_Y3_N0; Fanout = 1; COMB Node = 'uart_16750:inst|iLSR_FIFOERR~77'Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X26_Y3_N1; Fanout = 2; REG Node = 'uart_16750:inst|iLSR_FIFOERR'Info: Total cell delay = 0.407 ns ( 100.00 % )Info: - Smallest register to register requirement is 0.016 nsInfo: + Hold relationship between source and destination is 0.000 nsInfo: + Latch edge is 0.000 nsInfo: Clock period of Destination clock "CLK" is 30.003 ns with offset of 0.000 ns and duty cycle of 50Info: Multicycle Setup factor for Destination register is 1Info: Multicycle Hold factor for Destination register is 1Info: - Launch edge is 0.000 nsInfo: Clock period of Source clock "CLK" is 30.003 ns with offset of 0.000 ns and duty cycle of 50Info: Multicycle Setup factor for Source register is 1Info: Multicycle Hold factor for Source register is 1Info: + Smallest clock skew is 0.000 nsInfo: + Longest clock path from clock "CLK" to destination register is 2.360 nsInfo: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK'Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl'Info: 3: + IC(0.725 ns) + CELL(0.537 ns) = 2.360 ns; Loc. = LCFF_X26_Y3_N1; Fanout = 2; REG Node = 'uart_16750:inst|iLSR_FIFOERR'Info: Total cell delay = 1.516 ns ( 64.24 % )Info: Total interconnect delay = 0.844 ns ( 35.76 % )Info: - Shortest clock path from clock "CLK" to source register is 2.360 nsInfo: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK'Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl'Info: 3: + IC(0.725 ns) + CELL(0.537 ns) = 2.360 ns; Loc. = LCFF_X26_Y3_N1; Fanout = 2; REG Node = 'uart_16750:inst|iLSR_FIFOERR'Info: Total cell delay = 1.516 ns ( 64.24 % )Info: Total interconnect delay = 0.844 ns ( 35.76 % )Info: - Micro clock to output delay of source is 0.250 nsInfo: + Micro hold delay of destination is 0.266 nsInfo: Slack time is 2.58 ns for clock "CLK" between source pin "WR" and destination register "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff"Info: + tsu requirement for source pin and destination register is 10.000 nsInfo: - tsu from clock to input pin is 7.420 nsInfo: + Longest pin to register delay is 9.802 nsInfo: 1: + IC(0.000 ns) + CELL(0.822 ns) = 0.822 ns; Loc. = PIN_E14; Fanout = 3; PIN Node = 'WR'Info: 2: + IC(4.183 ns) + CELL(0.436 ns) = 5.441 ns; Loc. = LCCOMB_X25_Y5_N14; Fanout = 6; COMB Node = 'uart_16750:inst|iLCRWrite~27'Info: 3: + IC(0.275 ns) + CELL(0.416 ns) = 6.132 ns; Loc. = LCCOMB_X25_Y5_N30; Fanout = 4; COMB Node = 'uart_16750:inst|iTHRWrite~26'Info: 4: + IC(0.734 ns) + CELL(0.150 ns) = 7.016 ns; Loc. = LCCOMB_X25_Y5_N18; Fanout = 16; COMB Node = 'uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_wreq~186'Info: 5: + IC(0.959 ns) + CELL(0.275 ns) = 8.250 ns; Loc. = LCCOMB_X21_Y5_N0; Fanout = 1; COMB Node = 'uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_will_be_1~161'Info: 6: + IC(0.256 ns) + CELL(0.416 ns) = 8.922 ns; Loc. = LCCOMB_X21_Y5_N10; Fanout = 2; COMB Node = 'uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_will_be_1~162'Info: 7: + IC(0.646 ns) + CELL(0.150 ns) = 9.718 ns; Loc. = LCCOMB_X21_Y5_N4; Fanout = 1; COMB Node = 'uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff~16'Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 9.802 ns; Loc. = LCFF_X21_Y5_N5; Fanout = 17; REG Node = 'uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff'Info: Total cell delay = 2.749 ns ( 28.05 % )Info: Total interconnect delay = 7.053 ns ( 71.95 % )Info: + Micro setup delay of destination is -0.036 nsInfo: - Shortest clock path from clock "CLK" to destination register is 2.346 nsInfo: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK'Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl'Info: 3: + IC(0.711 ns) + CELL(0.537 ns) = 2.346 ns; Loc. = LCFF_X21_Y5_N5; Fanout = 17; REG Node = 'uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff'Info: Total cell delay = 1.516 ns ( 64.62 % )Info: Total interconnect delay = 0.830 ns ( 35.38 % )Info: Slack time is 2.856 ns for clock "CLK" between source memory "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5" and destination pin "DOUT[3]"Info: + tco requirement for source memory and destination pin is 15.000 nsInfo: - tco from clock to output pin is 12.144 nsInfo: + Longest clock path from clock "CLK" to source memory is 2.447 nsInfo: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK'Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl'Info: 3: + IC(0.660 ns) + CELL(0.689 ns) = 2.447 ns; Loc. = M4K_X23_Y3; Fanout = 11; MEM Node = 'uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5'Info: Total cell delay = 1.668 ns ( 68.17 % )Info: Total interconnect delay = 0.779 ns ( 31.83 % )Info: + Micro clock to output delay of source is 0.209 nsInfo: + Longest memory to pin delay is 9.488 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X23_Y3; Fanout = 11; MEM Node = 'uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5'Info: 2: + IC(0.000 ns) + CELL(2.991 ns) = 2.991 ns; Loc. = M4K_X23_Y3; Fanout = 1; MEM Node = 'uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|q_b[3]'Info: 3: + IC(0.421 ns) + CELL(0.150 ns) = 3.562 ns; Loc. = LCCOMB_X24_Y3_N2; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~35'Info: 4: + IC(0.440 ns) + CELL(0.150 ns) = 4.152 ns; Loc. = LCCOMB_X25_Y3_N16; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~36'Info: 5: + IC(0.252 ns) + CELL(0.275 ns) = 4.679 ns; Loc. = LCCOMB_X25_Y3_N28; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~37'Info: 6: + IC(0.246 ns) + CELL(0.150 ns) = 5.075 ns; Loc. = LCCOMB_X25_Y3_N22; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~38'Info: 7: + IC(1.345 ns) + CELL(3.068 ns) = 9.488 ns; Loc. = PIN_T11; Fanout = 0; PIN Node = 'DOUT[3]'Info: Total cell delay = 6.784 ns ( 71.50 % )Info: Total interconnect delay = 2.704 ns ( 28.50 % )Info: Longest tpd from source pin "A[1]" to destination pin "DOUT[3]" is 14.563 nsInfo: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_F16; Fanout = 15; PIN Node = 'A[1]'Info: 2: + IC(5.385 ns) + CELL(0.398 ns) = 6.615 ns; Loc. = LCCOMB_X24_Y5_N0; Fanout = 14; COMB Node = 'uart_16750:inst|Mux0~160'Info: 3: + IC(1.607 ns) + CELL(0.415 ns) = 8.637 ns; Loc. = LCCOMB_X24_Y3_N2; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~35'Info: 4: + IC(0.440 ns) + CELL(0.150 ns) = 9.227 ns; Loc. = LCCOMB_X25_Y3_N16; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~36'Info: 5: + IC(0.252 ns) + CELL(0.275 ns) = 9.754 ns; Loc. = LCCOMB_X25_Y3_N28; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~37'Info: 6: + IC(0.246 ns) + CELL(0.150 ns) = 10.150 ns; Loc. = LCCOMB_X25_Y3_N22; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~38'Info: 7: + IC(1.345 ns) + CELL(3.068 ns) = 14.563 ns; Loc. = PIN_T11; Fanout = 0; PIN Node = 'DOUT[3]'Info: Total cell delay = 5.288 ns ( 36.31 % )Info: Total interconnect delay = 9.275 ns ( 63.69 % )Info: th for register "uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd" (data pin = "WR", clock pin = "CLK") is -2.602 nsInfo: + Longest clock path from clock "CLK" to destination register is 2.352 nsInfo: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK'Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl'Info: 3: + IC(0.717 ns) + CELL(0.537 ns) = 2.352 ns; Loc. = LCFF_X25_Y5_N5; Fanout = 2; REG Node = 'uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd'Info: Total cell delay = 1.516 ns ( 64.46 % )Info: Total interconnect delay = 0.836 ns ( 35.54 % )Info: + Micro hold delay of destination is 0.266 nsInfo: - Shortest pin to register delay is 5.220 nsInfo: 1: + IC(0.000 ns) + CELL(0.822 ns) = 0.822 ns; Loc. = PIN_E14; Fanout = 3; PIN Node = 'WR'Info: 2: + IC(4.164 ns) + CELL(0.150 ns) = 5.136 ns; Loc. = LCCOMB_X25_Y5_N4; Fanout = 1; COMB Node = 'uart_16750:inst|iCSWR'Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 5.220 ns; Loc. = LCFF_X25_Y5_N5; Fanout = 2; REG Node = 'uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd'Info: Total cell delay = 1.056 ns ( 20.23 % )Info: Total interconnect delay = 4.164 ns ( 79.77 % )Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details.Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warningsInfo: Peak virtual memory: 127 megabytesInfo: Processing ended: Tue Feb 17 23:02:39 2009Info: Elapsed time: 00:00:00Info: Total CPU time (on all processors): 00:00:01