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Subversion Repositories uart16750
[/] [uart16750/] [trunk/] [syn/] [Altera/] [CycloneII/] [UART16750.tan.summary] - Rev 16
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Timing Analyzer Summary
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Type : Worst-case tsu
Slack : 2.580 ns
Required Time : 10.000 ns
Actual Time : 7.420 ns
From : WR
To : uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff
From Clock : --
To Clock : CLK
Failed Paths : 0
Type : Worst-case tco
Slack : 2.856 ns
Required Time : 15.000 ns
Actual Time : 12.144 ns
From : uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5
To : DOUT[3]
From Clock : CLK
To Clock : --
Failed Paths : 0
Type : Worst-case tpd
Slack : N/A
Required Time : None
Actual Time : 14.563 ns
From : A[1]
To : DOUT[3]
From Clock : --
To Clock : --
Failed Paths : 0
Type : Worst-case th
Slack : N/A
Required Time : None
Actual Time : -2.602 ns
From : WR
To : uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd
From Clock : --
To Clock : CLK
Failed Paths : 0
Type : Clock Setup: 'CLK'
Slack : 22.036 ns
Required Time : 33.33 MHz ( period = 30.003 ns )
Actual Time : 125.52 MHz ( period = 7.967 ns )
From : uart_16750:inst|iTSR[3]
To : uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4]
From Clock : CLK
To Clock : CLK
Failed Paths : 0
Type : Clock Hold: 'CLK'
Slack : 0.391 ns
Required Time : 33.33 MHz ( period = 30.003 ns )
Actual Time : N/A
From : uart_16750:inst|iLSR_FIFOERR
To : uart_16750:inst|iLSR_FIFOERR
From Clock : CLK
To Clock : CLK
Failed Paths : 0
Type : Total number of failed paths
Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0
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