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URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [syn/] [xilinx/] [uart2bus.xise] - Rev 3

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <header>
    <!-- ISE source project file created by Project Navigator.             -->
    <!--                                                                   -->
    <!-- This file contains project source information including a list of -->
    <!-- project source files, project and process properties.  This file, -->
    <!-- along with the project source files, is sufficient to open and    -->
    <!-- implement in ISE Project Navigator.                               -->
    <!--                                                                   -->
    <!-- Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved. -->
  </header>

  <version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>

  <files>
    <file xil_pn:name="../../rtl/baud_gen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../rtl/uart2bus_top.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../rtl/uart_parser.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../rtl/uart_rx.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../rtl/uart_top.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="../../rtl/uart_tx.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="uart2bus_top.ucf" xil_pn:type="FILE_UCF"/>
  </files>

  <properties>
    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3"/>
    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3"/>
    <property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
    <property xil_pn:name="Device" xil_pn:value="xc3s50"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3"/>
    <property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
    <property xil_pn:name="Implementation Top" xil_pn:value="Module|uart2bus_top"/>
    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart2bus_top"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="uart2bus"/>
    <property xil_pn:name="Package" xil_pn:value="pq208"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
    <property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-5"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
    <property xil_pn:name="Target UCF File Name" xil_pn:value="uart2bus_top.ucf"/>
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
    <property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
  </properties>

  <bindings/>

  <libraries/>

  <partitions>
    <partition xil_pn:name="/uart2bus_top"/>
  </partitions>

</project>

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