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https://opencores.org/ocsvn/uart2bus/uart2bus/trunk
Subversion Repositories uart2bus
[/] [uart2bus/] [trunk/] [vhdl/] [syn/] [xilinx/] [uart2bus.xise] - Rev 11
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xil_pn:valueState="default"/><property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/><property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/><property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/><property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/><property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/><property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/><property xil_pn:name="Rename Top Level Entity to" xil_pn:value="uart2BusTop" xil_pn:valueState="default"/><property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Report Paths by Endpoint" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/><property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/><property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/><property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/><property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="SAIF File Name" xil_pn:value="xpower_time_sim.saif" xil_pn:valueState="default"/><property xil_pn:name="SDK Export Directory" xil_pn:value="SDK_Export" xil_pn:valueState="default"/><property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/><property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/><property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/><property xil_pn:name="Setting Output File" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/><property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/><property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/><property xil_pn:name="Simulator" xil_pn:value="Modelsim-XE VHDL" xil_pn:valueState="non-default"/><property xil_pn:name="Simulator Path" xil_pn:value="C:/Modeltech_xe_starter/win32xoem" xil_pn:valueState="default"/><property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/><property xil_pn:name="Smart Guide File Name" xil_pn:value="uart2BusTop_guide.ncd" xil_pn:valueState="default"/><property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Specify Source Libraries Path" xil_pn:value="Search in Path" xil_pn:valueState="default"/><property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/><property xil_pn:name="Stamp Timing Model Filename" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/><property xil_pn:name="Starting Placer Cost Table (1-100) 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xil_pn:valueState="default"/><property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/><property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/><property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/><property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="User Rules File for Netlister Launcher" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/><property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/><property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Verilog Include Directories" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/><property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Work Directory" xil_pn:value="xst" xil_pn:valueState="default"/><property xil_pn:name="Working Directory" xil_pn:value="D:/design/uart2bus/syn/xilinx" xil_pn:valueState="non-default"/><property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="iMPACT Project File" xil_pn:value="Default" xil_pn:valueState="default"/><!-- --><!-- The following properties are for internal use only. These should not be modified.--><!-- --><property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_DesignName" xil_pn:value="uart2bus" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/><property xil_pn:name="PROP_PartitionCreateDelete" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PartitionForcePlacement" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PartitionForceSynth" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PartitionForceTranslate" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/></properties><bindings/><libraries/><partitions/></project>