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https://opencores.org/ocsvn/uart6551/uart6551/trunk
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[/] [uart6551/] [trunk/] [trunk/] [doc/] [uart6551.txt] - Rev 5
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|WISHBONE Datasheet
|WISHBONE SoC Architecture Specification, Revision B.3
|
|Description: Specifications:
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|General Description: UART core
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|Supported Cycles: SLAVE,READ/WRITE
| SLAVE,BLOCK READ/WRITE
| SLAVE,RMW
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|Data port, size: 32 bit
|Data port, granularity: 8 bit
|Data port, maximum operand size: 32 bit
|Data transfer ordering: Undefined
|Data transfer sequencing: Undefined
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|Clock frequency constraints: 100MHz for proper baud lookup
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|Supported signal list and Signal Name WISHBONE equiv.
|cross reference to equivalent ack_o ACK_O
|WISHBONE signals adr_i[1:0] ADR_I()
| clk_i CLK_I
| rst_i RST_I()
| dat_i(31:0) DAT_I()
| dat_o(31:0) DAT_O()
| cyc_i CYC_I
| stb_i STB_I
| we_i WE_I
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|Special requirements:
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