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<p><a href="classuart__wishbone__slave-members.html">List of all members.</a></p>
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Entities</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top"><a class="el" href="classuart__wishbone__slave_1_1_behavioral.html">Behavioral</a>  </td><td class="memItemRight" valign="bottom">architecture</td></tr>
<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Top <a class="el" href="classuart__wishbone__slave.html">uart_wishbone_slave</a> architecture. <a href="classuart__wishbone__slave_1_1_behavioral.html#details">More...</a><br/></td></tr>
<br/>
<br/>
<tr><td colspan="2"><h2><a name="Use Clauses"></a>
Use Clauses</h2></td></tr>
<tr class="memitem:ac442dca664056131bdaf5c92e4351e01"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac442dca664056131bdaf5c92e4351e01"></a>
<a class="el" href="classuart__wishbone__slave.html#ac442dca664056131bdaf5c92e4351e01">pkgDefinitions</a> </td><td class="memItemRight" valign="bottom"> <b>Package</b><em><a class="el" href="classpkg_definitions.html"> <pkgDefinitions></a></td></tr>
<tr class="memdesc:ac442dca664056131bdaf5c92e4351e01"><td class="mdescLeft"> </td><td class="mdescRight">Use CPU Definitions package. <br/></td></tr>
<tr><td colspan="2"><h2><a name="Ports"></a>
Ports</h2></td></tr>
<tr class="memitem:a4775682dc01dcbf48f20a731490ff2da"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4775682dc01dcbf48f20a731490ff2da"></a>
<a class="el" href="classuart__wishbone__slave.html#a4775682dc01dcbf48f20a731490ff2da">RST_I</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">STD_LOGIC</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:a4775682dc01dcbf48f20a731490ff2da"><td class="mdescLeft"> </td><td class="mdescRight">Reset Input. <br/></td></tr>
<tr class="memitem:aa26da3641303aaf250c88cbdf3d8a1a3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa26da3641303aaf250c88cbdf3d8a1a3"></a>
<a class="el" href="classuart__wishbone__slave.html#aa26da3641303aaf250c88cbdf3d8a1a3">CLK_I</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">STD_LOGIC</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:aa26da3641303aaf250c88cbdf3d8a1a3"><td class="mdescLeft"> </td><td class="mdescRight">Clock Input. <br/></td></tr>
<tr class="memitem:aca7516cbd7b6a93eac24e720fc01760c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aca7516cbd7b6a93eac24e720fc01760c"></a>
<a class="el" href="classuart__wishbone__slave.html#aca7516cbd7b6a93eac24e720fc01760c">ADR_I0</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">STD_LOGIC_VECTOR</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">1</span> <span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:aca7516cbd7b6a93eac24e720fc01760c"><td class="mdescLeft"> </td><td class="mdescRight">Address input. <br/></td></tr>
<tr class="memitem:ad423901fb91ee750587d52bd9ddb2001"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad423901fb91ee750587d52bd9ddb2001"></a>
<a class="el" href="classuart__wishbone__slave.html#ad423901fb91ee750587d52bd9ddb2001">DAT_I0</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">STD_LOGIC_VECTOR</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">31</span> <span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:ad423901fb91ee750587d52bd9ddb2001"><td class="mdescLeft"> </td><td class="mdescRight">Data Input 0. <br/></td></tr>
<tr class="memitem:a5779ba7b1bb275d5e56907020420ca27"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5779ba7b1bb275d5e56907020420ca27"></a>
<a class="el" href="classuart__wishbone__slave.html#a5779ba7b1bb275d5e56907020420ca27">DAT_O0</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">out</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">STD_LOGIC_VECTOR</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">31</span> <span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:a5779ba7b1bb275d5e56907020420ca27"><td class="mdescLeft"> </td><td class="mdescRight">Data Output 0. <br/></td></tr>
<tr class="memitem:a32a749c5f0d113303c3de1fa917b8f56"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a32a749c5f0d113303c3de1fa917b8f56"></a>
<a class="el" href="classuart__wishbone__slave.html#a32a749c5f0d113303c3de1fa917b8f56">WE_I</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">STD_LOGIC</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:a32a749c5f0d113303c3de1fa917b8f56"><td class="mdescLeft"> </td><td class="mdescRight">Write enable input. <br/></td></tr>
<tr class="memitem:af3bb8cfb2912c0d4ce792bd6c53d6a4c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af3bb8cfb2912c0d4ce792bd6c53d6a4c"></a>
<a class="el" href="classuart__wishbone__slave.html#af3bb8cfb2912c0d4ce792bd6c53d6a4c">STB_I</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">STD_LOGIC</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:af3bb8cfb2912c0d4ce792bd6c53d6a4c"><td class="mdescLeft"> </td><td class="mdescRight">Strobe input (Works like a chip select) <br/></td></tr>
<tr class="memitem:aeec8b0022ebb92b40f746bf13cf7319c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aeec8b0022ebb92b40f746bf13cf7319c"></a>
<a class="el" href="classuart__wishbone__slave.html#aeec8b0022ebb92b40f746bf13cf7319c">ACK_O</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">out</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">STD_LOGIC</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:aeec8b0022ebb92b40f746bf13cf7319c"><td class="mdescLeft"> </td><td class="mdescRight">Ack output. <br/></td></tr>
<tr class="memitem:aafe347fe5fc89efa63d92386f60c5f50"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aafe347fe5fc89efa63d92386f60c5f50"></a>
<a class="el" href="classuart__wishbone__slave.html#aafe347fe5fc89efa63d92386f60c5f50">serial_in</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:aafe347fe5fc89efa63d92386f60c5f50"><td class="mdescLeft"> </td><td class="mdescRight">Uart serial input. <br/></td></tr>
<tr class="memitem:ad55ceaa2b85f0ff8d37ba499fc620a61"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad55ceaa2b85f0ff8d37ba499fc620a61"></a>
<a class="el" href="classuart__wishbone__slave.html#ad55ceaa2b85f0ff8d37ba499fc620a61">data_Avaible</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">out</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:ad55ceaa2b85f0ff8d37ba499fc620a61"><td class="mdescLeft"> </td><td class="mdescRight">Flag to indicate data avaible. <br/></td></tr>
<tr class="memitem:ae336ee759d06264b8275495aae8cfefa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae336ee759d06264b8275495aae8cfefa"></a>
<a class="el" href="classuart__wishbone__slave.html#ae336ee759d06264b8275495aae8cfefa">serial_out</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">out</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
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<hr/><a name="details" id="details"></a><h2>Detailed Description</h2>
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<p>Definition at line <a class="el" href="uart__wishbone__slave_8vhd_source.html#l00010">10</a> of file <a class="el" href="uart__wishbone__slave_8vhd_source.html">uart_wishbone_slave.vhd</a>.</p>
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<li>E:/uart_block/hdl/iseProject/<a class="el" href="uart__wishbone__slave_8vhd_source.html">uart_wishbone_slave.vhd</a></li>
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