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<a href="uart__control_8vhd.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001
<a name="l00003"></a>00003 <span class="vhdlkeyword">library </span><span class="keywordflow">IEEE</span>;
<a name="l00004"></a>00004 <span class="vhdlkeyword">use </span>IEEE.STD_LOGIC_1164.<span class="vhdlkeyword">ALL</span>;
<a name="l00005"></a>00005 <span class="vhdlkeyword">use </span>ieee.std_logic_unsigned.<span class="vhdlkeyword">all</span>;
<a name="l00006"></a>00006 <span class="vhdlkeyword">use </span>ieee.std_logic_arith.<span class="vhdlkeyword">all</span>;
<a name="l00007"></a>00007
<a name="l00009"></a><a class="code" href="classuart__control.html#ac442dca664056131bdaf5c92e4351e01">00009</a> <span class="vhdlkeyword">use </span>work.pkgDefinitions.<span class="vhdlkeyword">all</span>;
<a name="l00010"></a>00010
<a name="l00011"></a><a class="code" href="classuart__control.html">00011</a> <span class="keywordflow">entity </span><a class="code" href="classuart__control.html">uart_control</a> <span class="vhdlkeyword">is</span>
<a name="l00012"></a><a class="code" href="classuart__control.html#a9d3a5df2e98b99b950613d125404f7e7">00012</a> <span class="vhdlkeyword">Port</span> <span class="vhdlchar">(</span> <span class="vhdlchar"><a class="code" href="classuart__control.html#a9d3a5df2e98b99b950613d125404f7e7" title="Global reset.">rst</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00013"></a><a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e">00013</a> <span class="vhdlchar"><a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00014"></a><a class="code" href="classuart__control.html#a5d0f1fd17d4ada84491cbbcdff7bd59c">00014</a> <span class="vhdlchar"><a class="code" href="classuart__control.html#a5d0f1fd17d4ada84491cbbcdff7bd59c" title="Write enable.">WE</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00015"></a><a class="code" href="classuart__control.html#a26488fd3af03df7e52e89685254581d9">00015</a> reg_addr : <span class="vhdlkeyword">in</span> <span class="comment">std_logic_vector</span> (<span class="vhdllogic">1</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic">0</span>); --! <span class="vhdlkeyword">Register</span> address
<a name="l00016"></a><a class="code" href="classuart__control.html#ae66e1f3b5a7b302a165fd87d2ebf8008">00016</a> <span class="vhdlchar"><a class="code" href="classuart__control.html#ae66e1f3b5a7b302a165fd87d2ebf8008" title="Start (Strobe)">start</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00017"></a><a class="code" href="classuart__control.html#a4772fc34e10751f941e00c7f532d3a51">00017</a> <span class="vhdlchar"><a class="code" href="classuart__control.html#a4772fc34e10751f941e00c7f532d3a51" title="Done (ACK)">done</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00018"></a><a class="code" href="classuart__control.html#a6a4e14f575e5b97e6af7829108a9cdb6">00018</a> <span class="vhdlchar"><a class="code" href="classuart__control.html#a6a4e14f575e5b97e6af7829108a9cdb6" title="Data Input (Wishbone)">DAT_I</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic_vector</span> <span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00019"></a><a class="code" href="classuart__control.html#aa0441f210e0ee245a9ee654ee0ecb105">00019</a> <span class="vhdlchar"><a class="code" href="classuart__control.html#aa0441f210e0ee245a9ee654ee0ecb105" title="Data output (Wishbone)">DAT_O</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic_vector</span> <span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00020"></a><a class="code" href="classuart__control.html#ad78e0a527c5f5c8c3ffa83c438b6f61f">00020</a> <span class="vhdlchar"><a class="code" href="classuart__control.html#ad78e0a527c5f5c8c3ffa83c438b6f61f" title="Signal to control the baud rate frequency.">baud_wait</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic_vector</span> <span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00021"></a><a class="code" href="classuart__control.html#af5fbd616289aa28ef674937c72548374">00021</a> <span class="vhdlchar"><a class="code" href="classuart__control.html#af5fbd616289aa28ef674937c72548374" title="1 Byte to be send to serial_transmitter">data_byte_tx</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBits</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00022"></a><a class="code" href="classuart__control.html#a938ea181dcf736513f3743dcf22dbf85">00022</a> <span class="vhdlchar"><a class="code" href="classuart__control.html#a938ea181dcf736513f3743dcf22dbf85" title="1 Byte to be received by serial_receiver">data_byte_rx</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBits</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00023"></a><a class="code" href="classuart__control.html#af90e032a76aef85021ee288bbec12e11">00023</a> <span class="vhdlchar"><a class="code" href="classuart__control.html#af90e032a76aef85021ee288bbec12e11" title="Signal comming from serial_transmitter.">tx_data_sent</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00024"></a><a class="code" href="classuart__control.html#ac8df6578912d098bdb9f21cb0509fb63">00024</a> <span class="vhdlchar"><a class="code" href="classuart__control.html#ac8df6578912d098bdb9f21cb0509fb63" title="Signal to start sending serial data...">tx_start</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00025"></a><a class="code" href="classuart__control.html#a665e6854e6570b00bd7d35db2049f54f">00025</a> <span class="vhdlchar"><a class="code" href="classuart__control.html#a665e6854e6570b00bd7d35db2049f54f" title="Reset Communication blocks.">rst_comm_blocks</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00026"></a><a class="code" href="classuart__control.html#a0f38cbc4316d4bba03252027fe0fabc7">00026</a> <span class="vhdlchar"><a class="code" href="classuart__control.html#a0f38cbc4316d4bba03252027fe0fabc7" title="Signal comming from serial_receiver.">rx_data_ready</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span><span class="vhdlchar">)</span>;
<a name="l00027"></a>00027 <span class="vhdlkeyword">end</span> <span class="vhdlchar">uart_control</span>;
<a name="l00028"></a>00028
<a name="l00031"></a><a class="code" href="classuart__control_1_1_behavioral.html">00031</a> <span class="vhdlkeyword">architecture</span> Behavioral <span class="vhdlkeyword">of</span> <a class="code" href="classuart__control.html">uart_control</a> is
<a name="l00032"></a>00032 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">config_clk</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00033"></a>00033 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">config_baud</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00034"></a>00034 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">received_byte</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBits</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00035"></a>00035 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">byte_to_transmit</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBits</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00036"></a>00036
<a name="l00037"></a>00037 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">sigDivRst</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00038"></a>00038 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">sigDivDone</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00039"></a>00039 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">sigDivQuotient</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00040"></a>00040 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">sigDivNumerator</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00041"></a>00041 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">sigDivDividend</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00042"></a>00042 <span class="keyword"></span>
<a name="l00043"></a>00043 <span class="keyword">-- Signals used <span class="vhdlkeyword">to</span> control the <span class="vhdlkeyword">configuration</span></span>
<a name="l00044"></a>00044 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">startConfigBaud</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00045"></a>00045 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">startConfigClk</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00046"></a>00046 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">startDataSend</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00047"></a>00047 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">commBlocksInitiated</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00048"></a>00048 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">startReadReg</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00049"></a>00049 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">alreadyConfBaud</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00050"></a>00050 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">alreadyConfClk</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00051"></a>00051 <span class="keyword"></span>
<a name="l00052"></a>00052 <span class="keyword">-- Divisor <span class="vhdlkeyword">component</span></span>
<a name="l00053"></a>00053 <span class="vhdlkeyword">component</span> <a class="code" href="classdivisor.html">divisor</a> <span class="vhdlkeyword">is</span>
<a name="l00054"></a>00054 <span class="vhdlkeyword">Port</span> ( <a class="code" href="classdivisor.html#a0ddd7f10f240eabbaa5f593dc724676d" title="Reset input.">rst</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00055"></a>00055 <a class="code" href="classdivisor.html#afccc0679a700cd9acf53b87c41fee67a" title="Clock input.">clk</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00056"></a>00056 <a class="code" href="classdivisor.html#a72b864bee7e5df9aaa6663e15717ee2a" title="Division result (32 bits)">quotient</a> : <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC_VECTOR</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00057"></a>00057 <a class="code" href="classdivisor.html#a2e2b27233f56bb5217044913043942fa" title="Reminder result (32 bits)">reminder</a> : <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC_VECTOR</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00058"></a>00058 <a class="code" href="classdivisor.html#ad29d3fb6c6ea697db492c43d4a3630eb" title="Numerator (32 bits)">numerator</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC_VECTOR</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00059"></a>00059 <a class="code" href="classdivisor.html#a125151d21c7a62bc99907ddc72a7ebb1" title=""Divide by" number (32 bits)">divident</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC_VECTOR</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00060"></a>00060 done : <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC</span>);
<a name="l00061"></a>00061 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">component</span>;
<a name="l00062"></a>00062
<a name="l00063"></a>00063 <span class="vhdlkeyword">begin</span>
<a name="l00065"></a>00065 uDiv : <a class="code" href="classdivisor.html">divisor</a> <span class="vhdlkeyword">port</span> <span class="vhdlkeyword">map</span> (
<a name="l00066"></a>00066 <a class="code" href="classdivisor.html#a0ddd7f10f240eabbaa5f593dc724676d" title="Reset input.">rst</a> => sigDivRst,
<a name="l00067"></a>00067 <a class="code" href="classdivisor.html#afccc0679a700cd9acf53b87c41fee67a" title="Clock input.">clk</a> => <a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a> ,
<a name="l00068"></a>00068 <a class="code" href="classdivisor.html#a72b864bee7e5df9aaa6663e15717ee2a" title="Division result (32 bits)">quotient</a> => sigDivQuotient,
<a name="l00069"></a>00069 <a class="code" href="classdivisor.html#a2e2b27233f56bb5217044913043942fa" title="Reminder result (32 bits)">reminder</a> => <span class="vhdlkeyword">open</span>,<span class="keyword"> -- Indicates that this <span class="vhdlkeyword">port</span> will <span class="vhdlkeyword">not</span> be connected <span class="vhdlkeyword">to</span> anything</span>
<a name="l00070"></a>00070 <a class="code" href="classdivisor.html#ad29d3fb6c6ea697db492c43d4a3630eb" title="Numerator (32 bits)">numerator</a> => sigDivNumerator,
<a name="l00071"></a>00071 <a class="code" href="classdivisor.html#a125151d21c7a62bc99907ddc72a7ebb1" title=""Divide by" number (32 bits)">divident</a> => sigDivDividend,
<a name="l00072"></a>00072 done => sigDivDone
<a name="l00073"></a>00073 <span class="vhdlchar">)</span>;
<a name="l00074"></a>00074 <span class="keyword"></span>
<a name="l00075"></a>00075 <span class="keyword"> -- <span class="vhdlkeyword">Process</span> <span class="vhdlkeyword">to</span> handle the <span class="vhdlkeyword">of</span> writting the registers</span>
<a name="l00076"></a>00076 <span class="vhdlkeyword">process</span> (<a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a>)
<a name="l00077"></a>00077 <span class="vhdlkeyword"> begin</span><span class="keyword"></span>
<a name="l00078"></a>00078 <span class="keyword"> -- <span class="vhdlkeyword">On</span> the wishbone specification we should handle the reset synchronously</span>
<a name="l00079"></a>00079 <span class="vhdlkeyword">if</span> <span class="vhdlchar">rising_edge</span><span class="vhdlchar">(</span><span class="vhdlchar"><a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a></span><span class="vhdlchar">)</span> <span class="vhdlkeyword">then</span>
<a name="l00080"></a>00080 <span class="vhdlkeyword">if</span> <span class="vhdlchar"><a class="code" href="classuart__control.html#a9d3a5df2e98b99b950613d125404f7e7" title="Global reset.">rst</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span>
<a name="l00081"></a>00081 config_clk <= (<span class="vhdlkeyword">others</span> => '0');
<a name="l00082"></a>00082 config_baud <= (<span class="vhdlkeyword">others</span> => '0');
<a name="l00083"></a>00083 <span class="vhdlchar">byte_to_transmit</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span>;
<a name="l00084"></a>00084 <span class="vhdlchar">startConfigBaud</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00085"></a>00085 <span class="vhdlchar">startConfigClk</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00086"></a>00086 <span class="vhdlchar">startDataSend</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00087"></a>00087 <span class="vhdlchar">alreadyConfClk</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00088"></a>00088 <span class="vhdlchar">alreadyConfBaud</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00089"></a>00089 <span class="vhdlkeyword">elsif</span> <span class="vhdlchar">(</span><span class="vhdlchar"><a class="code" href="classuart__control.html#a5d0f1fd17d4ada84491cbbcdff7bd59c" title="Write enable.">WE</a></span> <span class="vhdlkeyword">and</span> <span class="vhdlchar"><a class="code" href="classuart__control.html#ae66e1f3b5a7b302a165fd87d2ebf8008" title="Start (Strobe)">start</a></span><span class="vhdlchar">)</span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span>
<a name="l00090"></a>00090 <span class="vhdlkeyword">case</span> <span class="vhdlchar"><a class="code" href="classuart__control.html#a26488fd3af03df7e52e89685254581d9" title="Register address.">reg_addr</a></span> <span class="vhdlkeyword">is</span>
<a name="l00091"></a>00091 <span class="vhdlkeyword">when</span> <span class="vhdllogic">"00"</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00092"></a>00092 config_clk <= DAT_I;
<a name="l00093"></a>00093 <span class="vhdlchar">startConfigClk</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00094"></a>00094 <span class="vhdlchar">startDataSend</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00095"></a>00095 <span class="vhdlchar">startConfigBaud</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00096"></a>00096 <span class="vhdlchar">alreadyConfClk</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00097"></a>00097 <span class="vhdlkeyword">when</span> <span class="vhdllogic">"01"</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00098"></a>00098 config_baud <= DAT_I;
<a name="l00099"></a>00099 <span class="vhdlchar">startConfigBaud</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00100"></a>00100 <span class="vhdlchar">startDataSend</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00101"></a>00101 <span class="vhdlchar">startConfigClk</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00102"></a>00102 <span class="vhdlchar">alreadyConfBaud</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00103"></a>00103 <span class="vhdlkeyword">when</span> <span class="vhdllogic">"10"</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00104"></a>00104 <span class="vhdlchar">byte_to_transmit</span> <span class="vhdlchar"><=</span> <span class="vhdlchar"><a class="code" href="classuart__control.html#a6a4e14f575e5b97e6af7829108a9cdb6" title="Data Input (Wishbone)">DAT_I</a></span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBits</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00105"></a>00105 <span class="vhdlchar">startConfigBaud</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00106"></a>00106 <span class="vhdlchar">startConfigClk</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00107"></a>00107 <span class="vhdlchar">startDataSend</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00108"></a>00108 <span class="vhdlkeyword">when</span> <span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00109"></a>00109 <span class="vhdlchar">startConfigBaud</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00110"></a>00110 <span class="vhdlchar">startConfigClk</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00111"></a>00111 <span class="vhdlchar">startDataSend</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00112"></a>00112 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">case</span>;
<a name="l00113"></a>00113 <span class="vhdlkeyword">else</span>
<a name="l00114"></a>00114 <span class="vhdlchar">startDataSend</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00115"></a>00115 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00116"></a>00116 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00117"></a>00117 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span>;
<a name="l00118"></a>00118 <span class="keyword"></span>
<a name="l00119"></a>00119 <span class="keyword"> -- <span class="vhdlkeyword">Process</span> <span class="vhdlkeyword">to</span> handle the reading <span class="vhdlkeyword">of</span> registers</span>
<a name="l00120"></a>00120 <span class="vhdlkeyword">process</span> (<a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a>)
<a name="l00121"></a>00121 <span class="vhdlkeyword"> begin</span><span class="keyword"></span>
<a name="l00122"></a>00122 <span class="keyword"> -- <span class="vhdlkeyword">On</span> the wishbone specification we should handle the reset synchronously</span>
<a name="l00123"></a>00123 <span class="vhdlkeyword">if</span> <span class="vhdlchar">rising_edge</span><span class="vhdlchar">(</span><span class="vhdlchar"><a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a></span><span class="vhdlchar">)</span> <span class="vhdlkeyword">then</span>
<a name="l00124"></a>00124 <span class="vhdlkeyword">if</span> <span class="vhdlchar"><a class="code" href="classuart__control.html#a9d3a5df2e98b99b950613d125404f7e7" title="Global reset.">rst</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span>
<a name="l00125"></a>00125 <span class="vhdlchar"><a class="code" href="classuart__control.html#aa0441f210e0ee245a9ee654ee0ecb105" title="Data output (Wishbone)">DAT_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span> <span class="vhdlchar">'</span><span class="vhdlchar">Z</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span>;
<a name="l00126"></a>00126 <span class="vhdlchar">startReadReg</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00127"></a>00127 <span class="vhdlkeyword">elsif</span> <span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar"><a class="code" href="classuart__control.html#a5d0f1fd17d4ada84491cbbcdff7bd59c" title="Write enable.">WE</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">and</span> <span class="vhdlchar">(</span><span class="vhdlchar"><a class="code" href="classuart__control.html#ae66e1f3b5a7b302a165fd87d2ebf8008" title="Start (Strobe)">start</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">then</span>
<a name="l00128"></a>00128 <span class="vhdlchar">startReadReg</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00129"></a>00129 <span class="vhdlkeyword">case</span> <span class="vhdlchar"><a class="code" href="classuart__control.html#a26488fd3af03df7e52e89685254581d9" title="Register address.">reg_addr</a></span> <span class="vhdlkeyword">is</span>
<a name="l00130"></a>00130 <span class="vhdlkeyword">when</span> <span class="vhdllogic">"00"</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00131"></a>00131 <span class="vhdlchar"><a class="code" href="classuart__control.html#aa0441f210e0ee245a9ee654ee0ecb105" title="Data output (Wishbone)">DAT_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">config_clk</span>;
<a name="l00132"></a>00132 <span class="vhdlkeyword">when</span> <span class="vhdllogic">"01"</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00133"></a>00133 <span class="vhdlchar"><a class="code" href="classuart__control.html#aa0441f210e0ee245a9ee654ee0ecb105" title="Data output (Wishbone)">DAT_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">config_baud</span>;
<a name="l00134"></a>00134 <span class="vhdlkeyword">when</span> <span class="vhdllogic">"10"</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00135"></a>00135 <span class="vhdlchar"><a class="code" href="classuart__control.html#aa0441f210e0ee245a9ee654ee0ecb105" title="Data output (Wishbone)">DAT_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">,</span> <span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdlchar">nBits</span><span class="vhdlchar">)</span><span class="vhdlchar">)</span> <span class="vhdlchar">&</span> <span class="vhdlchar">byte_to_transmit</span>;
<a name="l00136"></a>00136 <span class="vhdlkeyword">when</span> <span class="vhdllogic">"11"</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00137"></a>00137 <span class="vhdlchar"><a class="code" href="classuart__control.html#aa0441f210e0ee245a9ee654ee0ecb105" title="Data output (Wishbone)">DAT_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">,</span> <span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdlchar">nBits</span><span class="vhdlchar">)</span><span class="vhdlchar">)</span> <span class="vhdlchar">&</span> <span class="vhdlchar">received_byte</span>;
<a name="l00138"></a>00138 <span class="vhdlkeyword">when</span> <span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00139"></a>00139 <span class="vhdlkeyword">null</span>;
<a name="l00140"></a>00140 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">case</span>;
<a name="l00141"></a>00141 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00142"></a>00142 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00143"></a>00143 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span>;
<a name="l00144"></a>00144 <span class="keyword"></span>
<a name="l00145"></a>00145 <span class="keyword"> -- <span class="vhdlkeyword">Process</span> that stores the data that comes from the serial receiver <span class="vhdlkeyword">block</span></span>
<a name="l00146"></a>00146 <span class="vhdlkeyword">process</span> (<a class="code" href="classuart__control.html#a0f38cbc4316d4bba03252027fe0fabc7" title="Signal comming from serial_receiver.">rx_data_ready</a>)
<a name="l00147"></a>00147 <span class="vhdlkeyword"> begin</span>
<a name="l00148"></a>00148 <span class="vhdlkeyword">if</span> <span class="vhdlchar">rising_edge</span><span class="vhdlchar">(</span><span class="vhdlchar"><a class="code" href="classuart__control.html#a0f38cbc4316d4bba03252027fe0fabc7" title="Signal comming from serial_receiver.">rx_data_ready</a></span><span class="vhdlchar">)</span> <span class="vhdlkeyword">then</span>
<a name="l00149"></a>00149 <span class="vhdlchar">received_byte</span> <span class="vhdlchar"><=</span> <span class="vhdlchar"><a class="code" href="classuart__control.html#a938ea181dcf736513f3743dcf22dbf85" title="1 Byte to be received by serial_receiver">data_byte_rx</a></span>;
<a name="l00150"></a>00150 <span class="vhdlkeyword">else</span>
<a name="l00151"></a>00151 <span class="vhdlchar">received_byte</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">received_byte</span>;
<a name="l00152"></a>00152 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00153"></a>00153 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span>;
<a name="l00154"></a>00154 <span class="keyword"></span>
<a name="l00155"></a>00155 <span class="keyword"> -- <span class="vhdlkeyword">Process</span> <span class="vhdlkeyword">to</span> send data over the serial transmitter</span>
<a name="l00156"></a>00156 <span class="vhdlkeyword">process</span> (<a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a>)
<a name="l00157"></a>00157 <span class="vhdlkeyword">variable</span> <span class="vhdlchar">sendDataStates</span> <span class="vhdlchar">:</span> <span class="vhdlchar">sendByte</span>;
<a name="l00158"></a>00158 <span class="vhdlkeyword"> begin</span>
<a name="l00159"></a>00159 <span class="vhdlkeyword">if</span> <span class="vhdlchar">rising_edge</span><span class="vhdlchar">(</span><span class="vhdlchar"><a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a></span><span class="vhdlchar">)</span> <span class="vhdlkeyword">then</span>
<a name="l00160"></a>00160 <span class="vhdlkeyword">if</span> <span class="vhdlchar">(</span><span class="vhdlchar"><a class="code" href="classuart__control.html#a9d3a5df2e98b99b950613d125404f7e7" title="Global reset.">rst</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">then</span>
<a name="l00161"></a>00161 <span class="vhdlchar">sendDataStates</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">idle</span>;
<a name="l00162"></a>00162 <span class="vhdlkeyword">else</span>
<a name="l00163"></a>00163 <span class="vhdlkeyword">case</span> <span class="vhdlchar">sendDataStates</span> <span class="vhdlkeyword">is</span>
<a name="l00164"></a>00164 <span class="vhdlkeyword">when</span> <span class="vhdlchar">idle</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00165"></a>00165 <span class="vhdlkeyword">if</span> <span class="vhdlchar">commBlocksInitiated</span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">and</span> <span class="vhdlchar">startDataSend</span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span>
<a name="l00166"></a>00166 <span class="vhdlchar">sendDataStates</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">prepare_byte</span>;
<a name="l00167"></a>00167 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00168"></a>00168
<a name="l00169"></a>00169 <span class="vhdlkeyword">when</span> <span class="vhdlchar">prepare_byte</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00170"></a>00170 <span class="vhdlchar"><a class="code" href="classuart__control.html#af5fbd616289aa28ef674937c72548374" title="1 Byte to be send to serial_transmitter">data_byte_tx</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">byte_to_transmit</span>;
<a name="l00171"></a>00171 <span class="vhdlchar"><a class="code" href="classuart__control.html#ac8df6578912d098bdb9f21cb0509fb63" title="Signal to start sending serial data...">tx_start</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00172"></a>00172 <span class="vhdlchar">sendDataStates</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">start_sending</span>;
<a name="l00173"></a>00173
<a name="l00174"></a>00174 <span class="vhdlkeyword">when</span> <span class="vhdlchar">start_sending</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00175"></a>00175 <span class="vhdlchar"><a class="code" href="classuart__control.html#ac8df6578912d098bdb9f21cb0509fb63" title="Signal to start sending serial data...">tx_start</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00176"></a>00176 <span class="vhdlchar">sendDataStates</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">wait_completion</span>;
<a name="l00177"></a>00177
<a name="l00178"></a>00178 <span class="vhdlkeyword">when</span> <span class="vhdlchar">wait_completion</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00179"></a>00179 <span class="vhdlkeyword">if</span> <span class="vhdlchar"><a class="code" href="classuart__control.html#af90e032a76aef85021ee288bbec12e11" title="Signal comming from serial_transmitter.">tx_data_sent</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span>
<a name="l00180"></a>00180 <span class="vhdlchar">sendDataStates</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">idle</span>;
<a name="l00181"></a>00181 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00182"></a>00182 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">case</span>;
<a name="l00183"></a>00183 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00184"></a>00184 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00185"></a>00185 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span>;
<a name="l00186"></a>00186 <span class="keyword"></span>
<a name="l00187"></a>00187 <span class="keyword"> -- <span class="vhdlkeyword">Process</span> <span class="vhdlkeyword">to</span> send the ACK <span class="vhdlkeyword">signal</span>, remember that optimally this ACK should be as fast as possible</span><span class="keyword"></span>
<a name="l00188"></a>00188 <span class="keyword"> -- <span class="vhdlkeyword">to</span> avoid locking the <span class="vhdlkeyword">bus</span>, <span class="vhdlkeyword">on</span> this <span class="vhdlkeyword">case</span> <span class="vhdlkeyword">if</span> you send a more bytes <span class="vhdlkeyword">then</span> you can transmit the ideal</span><span class="keyword"></span>
<a name="l00189"></a>00189 <span class="keyword"> -- <span class="vhdlkeyword">is</span> <span class="vhdlkeyword">to</span> create an error flag <span class="vhdlkeyword">to</span> indicate overrun.</span><span class="keyword"></span>
<a name="l00190"></a>00190 <span class="keyword"> -- <span class="vhdlkeyword">On</span> this <span class="vhdlkeyword">case</span> <span class="vhdlkeyword">on</span> any attempt <span class="vhdlkeyword">of</span> reading <span class="vhdlkeyword">or</span> writting <span class="vhdlkeyword">on</span> registers we will be lock <span class="vhdlkeyword">on</span> </span><span class="vhdllogic">1</span> cycle
<a name="l00191"></a>00191 <span class="vhdlkeyword">process</span> (<a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a>, <a class="code" href="classuart__control.html#a9d3a5df2e98b99b950613d125404f7e7" title="Global reset.">rst</a>, startConfigBaud, startConfigClk, startDataSend, startReadReg )
<a name="l00192"></a>00192 <span class="vhdlkeyword">variable</span> <span class="vhdlchar">joinSignal</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">3</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00193"></a>00193 <span class="vhdlkeyword">variable</span> <span class="vhdlchar">cont_steps</span> <span class="vhdlchar">:</span> <span class="comment">integer</span> <span class="vhdlkeyword">range</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span> <span class="vhdlkeyword">to</span> <span class="vhdllogic"></span><span class="vhdllogic">3</span>;
<a name="l00194"></a>00194 <span class="vhdlkeyword"> begin</span>
<a name="l00195"></a>00195 <span class="vhdlkeyword">if</span> <span class="vhdlchar">rising_edge</span><span class="vhdlchar">(</span><span class="vhdlchar"><a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a></span><span class="vhdlchar">)</span> <span class="vhdlkeyword">then</span>
<a name="l00196"></a>00196 <span class="vhdlkeyword">if</span> <span class="vhdlchar"><a class="code" href="classuart__control.html#a9d3a5df2e98b99b950613d125404f7e7" title="Global reset.">rst</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span>
<a name="l00197"></a>00197 <span class="vhdlchar"><a class="code" href="classuart__control.html#a4772fc34e10751f941e00c7f532d3a51" title="Done (ACK)">done</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00198"></a>00198 <span class="vhdlchar">cont_steps</span> <span class="vhdlchar">:=</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>;
<a name="l00199"></a>00199 <span class="vhdlkeyword">else</span>
<a name="l00200"></a>00200 <span class="vhdlchar">joinSignal</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">startConfigBaud</span> <span class="vhdlchar">&</span> <span class="vhdlchar">startConfigClk</span> <span class="vhdlchar">&</span> <span class="vhdlchar">startDataSend</span> <span class="vhdlchar">&</span> <span class="vhdlchar">startReadReg</span>;
<a name="l00201"></a>00201 <span class="vhdlkeyword">if</span> <span class="vhdlchar">(</span><span class="vhdlchar">joinSignal</span> <span class="vhdlchar">=</span> <span class="vhdllogic">"0000"</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">then</span>
<a name="l00202"></a>00202 <span class="vhdlchar"><a class="code" href="classuart__control.html#a4772fc34e10751f941e00c7f532d3a51" title="Done (ACK)">done</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00203"></a>00203 <span class="vhdlkeyword">else</span>
<a name="l00204"></a>00204 <span class="vhdlkeyword">case</span> <span class="vhdlchar">cont_steps</span> <span class="vhdlkeyword">is</span>
<a name="l00205"></a>00205 <span class="vhdlkeyword">when</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00206"></a>00206 <span class="vhdlkeyword">if</span> <span class="vhdlchar"><a class="code" href="classuart__control.html#ae66e1f3b5a7b302a165fd87d2ebf8008" title="Start (Strobe)">start</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span>
<a name="l00207"></a>00207 <span class="vhdlchar"><a class="code" href="classuart__control.html#a4772fc34e10751f941e00c7f532d3a51" title="Done (ACK)">done</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00208"></a>00208 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00209"></a>00209 <span class="vhdlkeyword">when</span> <span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00210"></a>00210 <span class="vhdlchar"><a class="code" href="classuart__control.html#a4772fc34e10751f941e00c7f532d3a51" title="Done (ACK)">done</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00211"></a>00211 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">case</span>;
<a name="l00212"></a>00212
<a name="l00213"></a>00213 <span class="vhdlkeyword">if</span> <span class="vhdlchar">cont_steps</span> <span class="vhdlchar"><</span> <span class="vhdllogic"></span><span class="vhdllogic">2</span> <span class="vhdlkeyword">then</span>
<a name="l00214"></a>00214 <span class="vhdlchar">cont_steps</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">cont_steps</span> <span class="vhdlchar">+</span> <span class="vhdllogic"></span><span class="vhdllogic">1</span>;
<a name="l00215"></a>00215 <span class="vhdlkeyword">else</span>
<a name="l00216"></a>00216 <span class="vhdlchar">cont_steps</span> <span class="vhdlchar">:=</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>;
<a name="l00217"></a>00217 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00218"></a>00218 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00219"></a>00219 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00220"></a>00220 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00221"></a>00221 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span>;
<a name="l00222"></a>00222 <span class="keyword"></span>
<a name="l00223"></a>00223 <span class="keyword"> -- <span class="vhdlkeyword">Process</span> <span class="vhdlkeyword">to</span> calculate the amount <span class="vhdlkeyword">of</span> cycles <span class="vhdlkeyword">to</span> <span class="vhdlkeyword">wait</span> (clock_speed / desired_baud), <span class="vhdlkeyword">and</span> initiate the board</span>
<a name="l00224"></a>00224 <span class="vhdlkeyword">process</span> (alreadyConfClk,alreadyConfBaud, <a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a>)
<a name="l00225"></a>00225 <span class="vhdlkeyword">variable</span> <span class="vhdlchar">cont_steps</span> <span class="vhdlchar">:</span> <span class="comment">integer</span> <span class="vhdlkeyword">range</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span> <span class="vhdlkeyword">to</span> <span class="vhdllogic"></span><span class="vhdllogic">3</span>;
<a name="l00226"></a>00226 <span class="vhdlkeyword"> begin</span>
<a name="l00227"></a>00227 <span class="vhdlkeyword">if</span> <span class="vhdlchar">(</span><span class="vhdlchar">alreadyConfClk</span> <span class="vhdlkeyword">and</span> <span class="vhdlchar">alreadyConfBaud</span><span class="vhdlchar">)</span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span>
<a name="l00228"></a>00228 <span class="vhdlchar">sigDivRst</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00229"></a>00229 <span class="vhdlchar">cont_steps</span> <span class="vhdlchar">:=</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>;
<a name="l00230"></a>00230 <span class="vhdlchar"><a class="code" href="classuart__control.html#ad78e0a527c5f5c8c3ffa83c438b6f61f" title="Signal to control the baud rate frequency.">baud_wait</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span>;
<a name="l00231"></a>00231 <span class="vhdlchar">commBlocksInitiated</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00232"></a>00232 <span class="vhdlkeyword">elsif</span> <span class="vhdlchar">rising_edge</span><span class="vhdlchar">(</span><span class="vhdlchar"><a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a></span><span class="vhdlchar">)</span> <span class="vhdlkeyword">then</span>
<a name="l00233"></a>00233 <span class="vhdlkeyword">if</span> <span class="vhdlchar">cont_steps</span> <span class="vhdlchar"><</span> <span class="vhdllogic"></span><span class="vhdllogic">3</span> <span class="vhdlkeyword">then</span>
<a name="l00234"></a>00234 <span class="vhdlchar">cont_steps</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">cont_steps</span> <span class="vhdlchar">+</span> <span class="vhdllogic"></span><span class="vhdllogic">1</span>;
<a name="l00235"></a>00235 <span class="vhdlkeyword">else</span>
<a name="l00236"></a>00236 <span class="vhdlchar">cont_steps</span> <span class="vhdlchar">:=</span> <span class="vhdllogic"></span><span class="vhdllogic">3</span>;
<a name="l00237"></a>00237 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00238"></a>00238
<a name="l00239"></a>00239 <span class="vhdlkeyword">case</span> <span class="vhdlchar">cont_steps</span> <span class="vhdlkeyword">is</span>
<a name="l00240"></a>00240 <span class="vhdlkeyword">when</span> <span class="vhdllogic"></span><span class="vhdllogic">1</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00241"></a>00241 <span class="vhdlchar">sigDivNumerator</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">config_clk</span>;
<a name="l00242"></a>00242 <span class="vhdlchar">sigDivDividend</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">config_baud</span>;
<a name="l00243"></a>00243 <span class="vhdlchar">sigDivRst</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00244"></a>00244 <span class="vhdlkeyword">when</span> <span class="vhdllogic"></span><span class="vhdllogic">2</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00245"></a>00245 <span class="vhdlchar">sigDivRst</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00246"></a>00246 <span class="vhdlkeyword">when</span> <span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00247"></a>00247 <span class="vhdlkeyword">null</span>;
<a name="l00248"></a>00248 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">case</span>;
<a name="l00249"></a>00249 <span class="keyword"></span>
<a name="l00250"></a>00250 <span class="keyword"> -- Enable the communication <span class="vhdlkeyword">block</span> <span class="vhdlkeyword">when</span> the baud <span class="vhdlkeyword">is</span> calculated</span>
<a name="l00251"></a>00251 <span class="vhdlkeyword">if</span> <span class="vhdlchar">sigDivDone</span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span>
<a name="l00252"></a>00252 <span class="vhdlchar"><a class="code" href="classuart__control.html#a665e6854e6570b00bd7d35db2049f54f" title="Reset Communication blocks.">rst_comm_blocks</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00253"></a>00253 <span class="vhdlchar"><a class="code" href="classuart__control.html#ad78e0a527c5f5c8c3ffa83c438b6f61f" title="Signal to control the baud rate frequency.">baud_wait</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">sigDivQuotient</span>;
<a name="l00254"></a>00254 <span class="vhdlchar">commBlocksInitiated</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00255"></a>00255 <span class="vhdlkeyword">else</span>
<a name="l00256"></a>00256 <span class="vhdlchar"><a class="code" href="classuart__control.html#ad78e0a527c5f5c8c3ffa83c438b6f61f" title="Signal to control the baud rate frequency.">baud_wait</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span>;
<a name="l00257"></a>00257 <span class="vhdlchar"><a class="code" href="classuart__control.html#a665e6854e6570b00bd7d35db2049f54f" title="Reset Communication blocks.">rst_comm_blocks</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00258"></a>00258 <span class="vhdlchar">commBlocksInitiated</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00259"></a>00259 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00260"></a>00260 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00261"></a>00261 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span>;
<a name="l00262"></a>00262
<a name="l00263"></a>00263 <span class="vhdlkeyword">end</span> <span class="vhdlchar">Behavioral</span>;
<a name="l00264"></a>00264
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