Subversion Repositories uart_block

\section{uart\-\_\-control Entity Reference}
\label{classuart__control}\index{uart\-\_\-control@{uart\-\_\-control}}
Inheritance diagram for uart\-\_\-control\-:\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[height=2.000000cm]{classuart__control}
\end{center}
\end{figure}
\subsection*{Entities}
\begin{DoxyCompactItemize}
\item 
{\bf Behavioral} architecture
\begin{DoxyCompactList}\small\item\em Uart control unit. \end{DoxyCompactList}\end{DoxyCompactItemize}
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\subsection*{Use Clauses}
 \begin{DoxyCompactItemize}
\item 
{\bf pkg\-Definitions}   \label{classuart__control_ac442dca664056131bdaf5c92e4351e01}
 
\begin{DoxyCompactList}\small\item\em Use C\-P\-U Definitions package. \end{DoxyCompactList}\end{DoxyCompactItemize}
\subsection*{Ports}
 \begin{DoxyCompactItemize}
\item 
{\bf rst}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic } \label{classuart__control_a9d3a5df2e98b99b950613d125404f7e7}
 
\begin{DoxyCompactList}\small\item\em Global reset. \end{DoxyCompactList}\item 
{\bf clk}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic } \label{classuart__control_aaa012193baea07aae07ac241afc38d4e}
 
\begin{DoxyCompactList}\small\item\em Global clock. \end{DoxyCompactList}\item 
{\bf W\-E}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic } \label{classuart__control_a5d0f1fd17d4ada84491cbbcdff7bd59c}
 
\begin{DoxyCompactList}\small\item\em Write enable. \end{DoxyCompactList}\item 
{\bf reg\-\_\-addr}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic\-\_\-vector (   1    downto    0  ) } \label{classuart__control_a26488fd3af03df7e52e89685254581d9}
 
\begin{DoxyCompactList}\small\item\em Register address. \end{DoxyCompactList}\item 
{\bf start}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic } \label{classuart__control_ae66e1f3b5a7b302a165fd87d2ebf8008}
 
\begin{DoxyCompactList}\small\item\em Start (Strobe) \end{DoxyCompactList}\item 
{\bf done}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic } \label{classuart__control_a4772fc34e10751f941e00c7f532d3a51}
 
\begin{DoxyCompactList}\small\item\em Done (A\-C\-K) \end{DoxyCompactList}\item 
{\bf D\-A\-T\-\_\-\-I}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic\-\_\-vector (  ( n\-Bits\-Large -\/   1  )    downto    0  ) } \label{classuart__control_a6a4e14f575e5b97e6af7829108a9cdb6}
 
\begin{DoxyCompactList}\small\item\em Data Input (Wishbone) \end{DoxyCompactList}\item 
{\bf D\-A\-T\-\_\-\-O}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic\-\_\-vector (  ( n\-Bits\-Large -\/   1  )    downto    0  ) } \label{classuart__control_aa0441f210e0ee245a9ee654ee0ecb105}
 
\begin{DoxyCompactList}\small\item\em Data output (Wishbone) \end{DoxyCompactList}\item 
{\bf baud\-\_\-wait}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic\-\_\-vector (  ( n\-Bits\-Large -\/   1  )    downto    0  ) } \label{classuart__control_ad78e0a527c5f5c8c3ffa83c438b6f61f}
 
\begin{DoxyCompactList}\small\item\em Signal to control the baud rate frequency. \end{DoxyCompactList}\item 
{\bf data\-\_\-byte\-\_\-tx}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic\-\_\-vector (  ( n\-Bits -\/   1  )    downto    0  ) } \label{classuart__control_af5fbd616289aa28ef674937c72548374}
 
\begin{DoxyCompactList}\small\item\em 1 Byte to be send to \doxyref{serial\-\_\-transmitter}{p.}{classserial__transmitter} \end{DoxyCompactList}\item 
{\bf data\-\_\-byte\-\_\-rx}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic\-\_\-vector (  ( n\-Bits -\/   1  )    downto    0  ) } \label{classuart__control_a938ea181dcf736513f3743dcf22dbf85}
 
\begin{DoxyCompactList}\small\item\em 1 Byte to be received by \doxyref{serial\-\_\-receiver}{p.}{classserial__receiver} \end{DoxyCompactList}\item 
{\bf tx\-\_\-data\-\_\-sent}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic } \label{classuart__control_af90e032a76aef85021ee288bbec12e11}
 
\begin{DoxyCompactList}\small\item\em Signal comming from \doxyref{serial\-\_\-transmitter}{p.}{classserial__transmitter}. \end{DoxyCompactList}\item 
{\bf tx\-\_\-start}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic } \label{classuart__control_ac8df6578912d098bdb9f21cb0509fb63}
 
\begin{DoxyCompactList}\small\item\em Signal to start sending serial data... \end{DoxyCompactList}\item 
{\bf rst\-\_\-comm\-\_\-blocks}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic } \label{classuart__control_a665e6854e6570b00bd7d35db2049f54f}
 
\begin{DoxyCompactList}\small\item\em Reset Communication blocks. \end{DoxyCompactList}\item 
{\bf rx\-\_\-data\-\_\-ready}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic } \label{classuart__control_a0f38cbc4316d4bba03252027fe0fabc7}
 
\begin{DoxyCompactList}\small\item\em Signal comming from \doxyref{serial\-\_\-receiver}{p.}{classserial__receiver}. \end{DoxyCompactList}\end{DoxyCompactItemize}
 
 
\subsection{Detailed Description}
 
 
Definition at line 11 of file uart\-\_\-control.\-vhd.
 
 
 
The documentation for this class was generated from the following file\-:\begin{DoxyCompactItemize}
\item 
E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf uart\-\_\-control.\-vhd}\end{DoxyCompactItemize}