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\section{uart\-\_\-wishbone\-\_\-slave Entity Reference}
\label{classuart__wishbone__slave}\index{uart\-\_\-wishbone\-\_\-slave@{uart\-\_\-wishbone\-\_\-slave}}
Inheritance diagram for uart\-\_\-wishbone\-\_\-slave\-:\begin{figure}[H]
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\includegraphics[height=2.000000cm]{classuart__wishbone__slave}
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\subsection*{Entities}
\begin{DoxyCompactItemize}
\item 
{\bf Behavioral} architecture
\begin{DoxyCompactList}\small\item\em Top \doxyref{uart\-\_\-wishbone\-\_\-slave}{p.}{classuart__wishbone__slave} architecture. \end{DoxyCompactList}\end{DoxyCompactItemize}
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\subsection*{Use Clauses}
 \begin{DoxyCompactItemize}
\item 
{\bf pkg\-Definitions}   \label{classuart__wishbone__slave_ac442dca664056131bdaf5c92e4351e01}
 
\begin{DoxyCompactList}\small\item\em Use C\-P\-U Definitions package. \end{DoxyCompactList}\end{DoxyCompactItemize}
\subsection*{Ports}
 \begin{DoxyCompactItemize}
\item 
{\bf R\-S\-T\-\_\-\-I}  {\bfseries {\bfseries in }} {\bfseries S\-T\-D\-\_\-\-L\-O\-G\-I\-C } \label{classuart__wishbone__slave_a4775682dc01dcbf48f20a731490ff2da}
 
\begin{DoxyCompactList}\small\item\em Reset Input. \end{DoxyCompactList}\item 
{\bf C\-L\-K\-\_\-\-I}  {\bfseries {\bfseries in }} {\bfseries S\-T\-D\-\_\-\-L\-O\-G\-I\-C } \label{classuart__wishbone__slave_aa26da3641303aaf250c88cbdf3d8a1a3}
 
\begin{DoxyCompactList}\small\item\em Clock Input. \end{DoxyCompactList}\item 
{\bf A\-D\-R\-\_\-\-I0}  {\bfseries {\bfseries in }} {\bfseries S\-T\-D\-\_\-\-L\-O\-G\-I\-C\-\_\-\-V\-E\-C\-T\-O\-R (   1    downto    0  ) } \label{classuart__wishbone__slave_aca7516cbd7b6a93eac24e720fc01760c}
 
\begin{DoxyCompactList}\small\item\em Address input. \end{DoxyCompactList}\item 
{\bf D\-A\-T\-\_\-\-I0}  {\bfseries {\bfseries in }} {\bfseries S\-T\-D\-\_\-\-L\-O\-G\-I\-C\-\_\-\-V\-E\-C\-T\-O\-R (   31    downto    0  ) } \label{classuart__wishbone__slave_ad423901fb91ee750587d52bd9ddb2001}
 
\begin{DoxyCompactList}\small\item\em Data Input 0. \end{DoxyCompactList}\item 
{\bf D\-A\-T\-\_\-\-O0}  {\bfseries {\bfseries out }} {\bfseries S\-T\-D\-\_\-\-L\-O\-G\-I\-C\-\_\-\-V\-E\-C\-T\-O\-R (   31    downto    0  ) } \label{classuart__wishbone__slave_a5779ba7b1bb275d5e56907020420ca27}
 
\begin{DoxyCompactList}\small\item\em Data Output 0. \end{DoxyCompactList}\item 
{\bf W\-E\-\_\-\-I}  {\bfseries {\bfseries in }} {\bfseries S\-T\-D\-\_\-\-L\-O\-G\-I\-C } \label{classuart__wishbone__slave_a32a749c5f0d113303c3de1fa917b8f56}
 
\begin{DoxyCompactList}\small\item\em Write enable input. \end{DoxyCompactList}\item 
{\bf S\-T\-B\-\_\-\-I}  {\bfseries {\bfseries in }} {\bfseries S\-T\-D\-\_\-\-L\-O\-G\-I\-C } \label{classuart__wishbone__slave_af3bb8cfb2912c0d4ce792bd6c53d6a4c}
 
\begin{DoxyCompactList}\small\item\em Strobe input (Works like a chip select) \end{DoxyCompactList}\item 
{\bf A\-C\-K\-\_\-\-O}  {\bfseries {\bfseries out }} {\bfseries S\-T\-D\-\_\-\-L\-O\-G\-I\-C } \label{classuart__wishbone__slave_aeec8b0022ebb92b40f746bf13cf7319c}
 
\begin{DoxyCompactList}\small\item\em Ack output. \end{DoxyCompactList}\item 
{\bf serial\-\_\-in}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic } \label{classuart__wishbone__slave_aafe347fe5fc89efa63d92386f60c5f50}
 
\begin{DoxyCompactList}\small\item\em Uart serial input. \end{DoxyCompactList}\item 
{\bf data\-\_\-\-Avaible}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic } \label{classuart__wishbone__slave_ad55ceaa2b85f0ff8d37ba499fc620a61}
 
\begin{DoxyCompactList}\small\item\em Flag to indicate data avaible. \end{DoxyCompactList}\item 
{\bf serial\-\_\-out}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic } \label{classuart__wishbone__slave_ae336ee759d06264b8275495aae8cfefa}
 
\end{DoxyCompactItemize}
 
 
\subsection{Detailed Description}
 
 
Definition at line 10 of file uart\-\_\-wishbone\-\_\-slave.\-vhd.
 
 
 
The documentation for this class was generated from the following file\-:\begin{DoxyCompactItemize}
\item 
E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf uart\-\_\-wishbone\-\_\-slave.\-vhd}\end{DoxyCompactItemize}