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https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [Sim_ConfigWishboneSlave.wcfg] - Rev 39
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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="pkgdefinitions" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
<top_module name="testuart_wishbone_slave" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="12" />
<wvobject fp_name="/testuart_wishbone_slave/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/adr_i0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_i0[1:0]</obj_property>
<obj_property name="ObjectShortName">adr_i0[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/dat_i0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_i0[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_i0[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/we_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we_i</obj_property>
<obj_property name="ObjectShortName">we_i</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">stb_i</obj_property>
<obj_property name="ObjectShortName">stb_i</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/serial_in" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">serial_in</obj_property>
<obj_property name="ObjectShortName">serial_in</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/dat_o0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_o0[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_o0[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ack_o</obj_property>
<obj_property name="ObjectShortName">ack_o</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/serial_out" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">serial_out</obj_property>
<obj_property name="ObjectShortName">serial_out</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/data_avaible" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">data_avaible</obj_property>
<obj_property name="ObjectShortName">data_avaible</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/clk_i_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">clk_i_period</obj_property>
<obj_property name="ObjectShortName">clk_i_period</obj_property>
</wvobject>
</wave_config>
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