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https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [_xmsgs/] [pn_parser.xmsgs] - Rev 20
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<?xml version="1.0" encoding="UTF-8"?><!-- IMPORTANT: This is an internal file that has been generated --><!-- by the Xilinx ISE software. Any direct editing or --><!-- changes made to this file may result in unpredictable --><!-- behavior or data corruption. It is strongly advised that --><!-- users do not edit the contents of this file. --><!-- --><!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --><messages><msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/uart_block/hdl/iseProject/baud_generator.vhd" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/uart_block/hdl/iseProject/divisor.vhd" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_control.vhd" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work</arg></msg></messages>
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