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<messages>
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">D</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">N</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">cycle_wait_oversample</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">half_cycle</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">half_cycle0</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="warning" file="Xst" num="1780" delta="old" >Signal &lt;<arg fmt="%s" index="1">byteReceived&lt;7&gt;</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">8</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data_byte</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;0&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;1&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;2&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;3&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;4&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;5&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;6&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;0&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;1&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;2&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;3&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;4&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;5&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>

<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;6&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>

<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">sigDivReminder</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">30</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">31</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">31</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">29</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">30</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">31</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_9&gt; &lt;cycle_wait_oversample_8&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_6&gt; &lt;cycle_wait_oversample_5&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_23</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_25&gt; &lt;cycle_wait_oversample_24&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_28</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_30&gt; &lt;cycle_wait_oversample_29&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;cycle_wait_oversample_0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_13</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_15&gt; &lt;cycle_wait_oversample_14&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_18</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_20&gt; &lt;cycle_wait_oversample_19&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_10&gt; &lt;cycle_wait_oversample_9&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_7&gt; &lt;cycle_wait_oversample_6&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_24</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_26&gt; &lt;cycle_wait_oversample_25&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_2&gt; &lt;cycle_wait_oversample_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_14</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_16&gt; &lt;cycle_wait_oversample_15&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_19</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_21&gt; &lt;cycle_wait_oversample_20&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_9</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_11&gt; &lt;cycle_wait_oversample_10&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_6</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_8&gt; &lt;cycle_wait_oversample_7&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_25</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_27&gt; &lt;cycle_wait_oversample_26&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_3&gt; &lt;cycle_wait_oversample_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_15</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_17&gt; &lt;cycle_wait_oversample_16&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_20</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_22&gt; &lt;cycle_wait_oversample_21&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_10</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_12&gt; &lt;cycle_wait_oversample_11&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_26</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_28&gt; &lt;cycle_wait_oversample_27&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_4&gt; &lt;cycle_wait_oversample_3&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_16</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_18&gt; &lt;cycle_wait_oversample_17&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_21</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_23&gt; &lt;cycle_wait_oversample_22&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_11</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_13&gt; &lt;cycle_wait_oversample_12&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_5&gt; &lt;cycle_wait_oversample_4&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_22</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_24&gt; &lt;cycle_wait_oversample_23&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_27</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_29&gt; &lt;cycle_wait_oversample_28&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_12</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_14&gt; &lt;cycle_wait_oversample_13&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_17</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_19&gt; &lt;cycle_wait_oversample_18&gt; </arg>
</msg>

<msg type="warning" file="Xst" num="2042" delta="old" >Unit <arg fmt="%s" index="1">serial_receiver</arg>: <arg fmt="%d" index="2">7</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/R_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_0</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_1</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_2</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_3</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_4</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_5</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_8</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_10</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_11</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_12</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_13</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_14</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_15</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_16</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_17</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_18</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_19</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_20</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_21</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_24</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_25</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_26</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_27</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_28</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_29</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_30</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>

<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>

</messages>