Subversion Repositories uart_block

Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_beh.prj work.testUart_control 
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_control.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 36628 KB
Fuse CPU Usage: 1070 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package pkgdefinitions
Compiling architecture behavioral of entity divisor [divisor_default]
Compiling architecture behavioral of entity uart_control [uart_control_default]
Compiling architecture behavior of entity testuart_control
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 10 VHDL Units
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe
Fuse Memory Usage: 85688 KB
Fuse CPU Usage: 1160 ms
GCC CPU Usage: 400 ms