Subversion Repositories uart_block

Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_beh.prj work.testSerial_receiver 
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 36024 KB
Fuse CPU Usage: 1080 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package pkgdefinitions
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
Compiling architecture behavior of entity testserial_receiver
Time Resolution for simulation is 1ps.
Compiled 6 VHDL Units
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe
Fuse Memory Usage: 79448 KB
Fuse CPU Usage: 1110 ms
GCC CPU Usage: 300 ms