Subversion Repositories uart_block

Running: fuse.exe -relaunch -intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave" 
ISim O.87xd (signature 0xc3576ebc)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16 
Determining compilation order of HDL files
Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/divisor.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/baud_generator.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_control.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work
WARNING:HDLCompiler:946 - "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port rst is neither a static name nor a globally static expression
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package pkgdefinitions
Compiling architecture behavioral of entity divisor [divisor_default]
Compiling architecture behavioral of entity uart_control [uart_control_default]
Compiling package numeric_std
Compiling architecture behavioral of entity baud_generator [baud_generator_default]
Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default]
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...]
Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default]
Compiling architecture behavior of entity testuart_wishbone_slave
Time Resolution for simulation is 1ps.
Compiled 21 VHDL Units
Built simulation executable E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe
Fuse Memory Usage: 37732 KB
Fuse CPU Usage: 405 ms