URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [iseProject.gise] - Rev 40
Compare with Previous | Blame | View Log
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"><!-- --><!-- For tool use only. Do not edit. --><!-- --><!-- ProjectNavigator created generated project file. --><!-- For use in tracking generated file and other information --><!-- allowing preservation of process status. --><!-- --><!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --><version xmlns="http://www.xilinx.com/XMLSchema">11.1</version><sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="iseProject.xise"/><files xmlns="http://www.xilinx.com/XMLSchema"><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="INTERCON_P2P.bld"/><file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="INTERCON_P2P.cmd_log"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="INTERCON_P2P.lso"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="INTERCON_P2P.ncd" xil_pn:subbranch="Par"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="INTERCON_P2P.ngc"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="INTERCON_P2P.ngd"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="INTERCON_P2P.ngr"/><file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="INTERCON_P2P.pad"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="INTERCON_P2P.par" xil_pn:subbranch="Par"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="INTERCON_P2P.pcf" xil_pn:subbranch="Map"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="INTERCON_P2P.prj"/><file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="INTERCON_P2P.ptwx"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="INTERCON_P2P.stx"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="INTERCON_P2P.syr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="INTERCON_P2P.twr" xil_pn:subbranch="Par"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="INTERCON_P2P.twx" xil_pn:subbranch="Par"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="INTERCON_P2P.unroutes" xil_pn:subbranch="Par"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="INTERCON_P2P.ut" xil_pn:subbranch="FPGAConfiguration"/><file xil_pn:fileType="FILE_XPI" xil_pn:name="INTERCON_P2P.xpi"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="INTERCON_P2P.xst"/><file xil_pn:fileType="FILE_BLIF" xil_pn:name="INTERCON_P2P_cs.blc"/><file xil_pn:fileType="FILE_NGC" xil_pn:name="INTERCON_P2P_cs.ngc"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="INTERCON_P2P_envsettings.html"/><file xil_pn:fileType="FILE_NCD" xil_pn:name="INTERCON_P2P_guide.ncd" xil_pn:origination="imported"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="INTERCON_P2P_map.map" xil_pn:subbranch="Map"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="INTERCON_P2P_map.mrp" xil_pn:subbranch="Map"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="INTERCON_P2P_map.ncd" xil_pn:subbranch="Map"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="INTERCON_P2P_map.ngm" xil_pn:subbranch="Map"/><file xil_pn:fileType="FILE_XRPT" xil_pn:name="INTERCON_P2P_map.xrpt"/><file xil_pn:fileType="FILE_XRPT" xil_pn:name="INTERCON_P2P_ngdbuild.xrpt"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="INTERCON_P2P_pad.csv" xil_pn:subbranch="Par"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="INTERCON_P2P_pad.txt" xil_pn:subbranch="Par"/><file xil_pn:fileType="FILE_XRPT" xil_pn:name="INTERCON_P2P_par.xrpt"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="INTERCON_P2P_summary.html"/><file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="INTERCON_P2P_summary.xml"/><file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="INTERCON_P2P_usage.xml"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="INTERCON_P2P_vhdl.prj"/><file xil_pn:fileType="FILE_XRPT" xil_pn:name="INTERCON_P2P_xst.xrpt"/><file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SERIALMASTER.cmd_log"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SERIALMASTER.lso"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="SERIALMASTER.ngc"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="SERIALMASTER.ngr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SERIALMASTER.prj"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="SERIALMASTER.stx"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SERIALMASTER.syr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SERIALMASTER.xst"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SERIALMASTER_vhdl.prj"/><file xil_pn:fileType="FILE_XRPT" xil_pn:name="SERIALMASTER_xst.xrpt"/><file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SYC0001a.cmd_log"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SYC0001a.lso"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="SYC0001a.ngc"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="SYC0001a.ngr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SYC0001a.prj"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="SYC0001a.stx"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SYC0001a.syr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SYC0001a.xst"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SYC0001a_vhdl.prj"/><file xil_pn:fileType="FILE_XRPT" xil_pn:name="SYC0001a_xst.xrpt"/><file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/><file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/><file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/><file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/><file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/><file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/><file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/><file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="baud_generator.cmd_log"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="baud_generator.lso"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="baud_generator.ngc"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="baud_generator.ngr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="baud_generator.prj"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="baud_generator.stx"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="baud_generator.syr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="baud_generator.xst"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="baud_generator_envsettings.html"/><file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="baud_generator_isim_beh.exe"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="baud_generator_summary.html"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="baud_generator_vhdl.prj"/><file xil_pn:fileType="FILE_XRPT" xil_pn:name="baud_generator_xst.xrpt"/><file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="divisor.cmd_log"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="divisor.lso"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="divisor.ngc"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="divisor.ngr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="divisor.prj"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="divisor.stx"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="divisor.syr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="divisor.xst"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="divisor_envsettings.html"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="divisor_summary.html"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="divisor_vhdl.prj"/><file xil_pn:fileType="FILE_XRPT" xil_pn:name="divisor_xst.xrpt"/><file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="intercon_p2p.bgn" xil_pn:subbranch="FPGAConfiguration"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="intercon_p2p.bit" xil_pn:subbranch="FPGAConfiguration"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="intercon_p2p.drc" xil_pn:subbranch="FPGAConfiguration"/><file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/><file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/><file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/><file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/><file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="serial_receiver.cmd_log"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="serial_receiver.lso"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="serial_receiver.ngc"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="serial_receiver.ngr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="serial_receiver.prj"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="serial_receiver.stx"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="serial_receiver.syr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="serial_receiver.xst"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="serial_receiver_envsettings.html"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="serial_receiver_summary.html"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="serial_receiver_vhdl.prj"/><file xil_pn:fileType="FILE_XRPT" xil_pn:name="serial_receiver_xst.xrpt"/><file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="serial_transmitter.cmd_log"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="serial_transmitter.lso"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="serial_transmitter.ngc"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="serial_transmitter.ngr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="serial_transmitter.prj"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="serial_transmitter.stx"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="serial_transmitter.syr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="serial_transmitter.xst"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="serial_transmitter_envsettings.html"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="serial_transmitter_summary.html"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="serial_transmitter_vhdl.prj"/><file xil_pn:fileType="FILE_XRPT" xil_pn:name="serial_transmitter_xst.xrpt"/><file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testBaud_generator_isim_beh.exe"/><file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDivisor_isim_beh.exe"/><file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_receiver_isim_beh.exe"/><file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testSerial_receiver_isim_beh.wdb"/><file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_transmitter_isim_beh.exe"/><file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testUart_communication_block_beh.prj"/><file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_communication_block_isim_beh.exe"/><file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testUart_communication_block_isim_beh.wdb"/><file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_control_isim_beh.exe"/><file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/><file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testUart_wishbone_slave_isim_beh.wdb"/><file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="uart_communication_blocks.cmd_log"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="uart_communication_blocks.lso"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="uart_communication_blocks.ngc"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="uart_communication_blocks.ngr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_communication_blocks.prj"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="uart_communication_blocks.stx"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="uart_communication_blocks.syr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="uart_communication_blocks.xst"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_communication_blocks_envsettings.html"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_communication_blocks_summary.html"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_communication_blocks_vhdl.prj"/><file xil_pn:fileType="FILE_XRPT" xil_pn:name="uart_communication_blocks_xst.xrpt"/><file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="uart_control.cmd_log"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="uart_control.lso"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="uart_control.ngc"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="uart_control.ngr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_control.prj"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="uart_control.stx"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="uart_control.syr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="uart_control.xst"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_control_envsettings.html"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_control_summary.html"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_control_vhdl.prj"/><file xil_pn:fileType="FILE_XRPT" xil_pn:name="uart_control_xst.xrpt"/><file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="uart_wishbone_slave.cmd_log"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="uart_wishbone_slave.lso"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="uart_wishbone_slave.ngc"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="uart_wishbone_slave.ngr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_wishbone_slave.prj"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="uart_wishbone_slave.stx"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="uart_wishbone_slave.syr"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="uart_wishbone_slave.xst"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_wishbone_slave_envsettings.html"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_wishbone_slave_summary.html"/><file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_wishbone_slave_vhdl.prj"/><file xil_pn:fileType="FILE_XRPT" xil_pn:name="uart_wishbone_slave_xst.xrpt"/><file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/><file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/><file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/><file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/><file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/><file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/></files><transforms xmlns="http://www.xilinx.com/XMLSchema"><transform xil_pn:end_ts="1335696912" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1335696912"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/></transform><transform xil_pn:end_ts="1336851239" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1336851239"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/><outfile xil_pn:name="INTERCON_P2P.vhd"/><outfile xil_pn:name="SERIALMASTER.vhd"/><outfile xil_pn:name="SYC0001a.vhd"/><outfile xil_pn:name="baud_generator.vhd"/><outfile xil_pn:name="divisor.vhd"/><outfile xil_pn:name="pkgDefinitions.vhd"/><outfile xil_pn:name="serial_receiver.vhd"/><outfile xil_pn:name="serial_transmitter.vhd"/><outfile xil_pn:name="testBaud_generator.vhd"/><outfile xil_pn:name="testDivisor.vhd"/><outfile xil_pn:name="testSerial_receiver.vhd"/><outfile xil_pn:name="testSerial_transmitter.vhd"/><outfile xil_pn:name="testUart_communication_block.vhd"/><outfile xil_pn:name="testUart_control.vhd"/><outfile xil_pn:name="testUart_wishbone_slave.vhd"/><outfile xil_pn:name="uart_communication_blocks.vhd"/><outfile xil_pn:name="uart_control.vhd"/><outfile xil_pn:name="uart_wishbone_slave.vhd"/></transform><transform xil_pn:end_ts="1336851239" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="1763861231223327121" xil_pn:start_ts="1336851239"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/></transform><transform xil_pn:end_ts="1336851239" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-3978620576363339309" xil_pn:start_ts="1336851239"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/></transform><transform xil_pn:end_ts="1336250441" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-7719148281395352834" xil_pn:start_ts="1336250441"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/></transform><transform xil_pn:end_ts="1336851239" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1336851239"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/><outfile xil_pn:name="INTERCON_P2P.vhd"/><outfile xil_pn:name="SERIALMASTER.vhd"/><outfile xil_pn:name="SYC0001a.vhd"/><outfile xil_pn:name="baud_generator.vhd"/><outfile xil_pn:name="divisor.vhd"/><outfile xil_pn:name="pkgDefinitions.vhd"/><outfile xil_pn:name="serial_receiver.vhd"/><outfile xil_pn:name="serial_transmitter.vhd"/><outfile xil_pn:name="testBaud_generator.vhd"/><outfile xil_pn:name="testDivisor.vhd"/><outfile xil_pn:name="testSerial_receiver.vhd"/><outfile xil_pn:name="testSerial_transmitter.vhd"/><outfile xil_pn:name="testUart_communication_block.vhd"/><outfile xil_pn:name="testUart_control.vhd"/><outfile xil_pn:name="testUart_wishbone_slave.vhd"/><outfile xil_pn:name="uart_communication_blocks.vhd"/><outfile xil_pn:name="uart_control.vhd"/><outfile xil_pn:name="uart_wishbone_slave.vhd"/></transform><transform xil_pn:end_ts="1336851242" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-1520739801670331996" xil_pn:start_ts="1336851239"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/><status xil_pn:value="OutOfDateForOutputs"/><status xil_pn:value="OutputChanged"/><outfile xil_pn:name="fuse.log"/><outfile xil_pn:name="isim"/><outfile xil_pn:name="isim.log"/><outfile xil_pn:name="testUart_communication_block_beh.prj"/><outfile xil_pn:name="testUart_communication_block_isim_beh.exe"/><outfile xil_pn:name="xilinxsim.ini"/></transform><transform xil_pn:end_ts="1336851242" xil_pn:in_ck="7043554240611338668" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-4664289266449917424" xil_pn:start_ts="1336851242"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/><status xil_pn:value="OutOfDateForOutputs"/><status xil_pn:value="OutputChanged"/><outfile xil_pn:name="isim.cmd"/><outfile xil_pn:name="isim.log"/><outfile xil_pn:name="testUart_communication_block_isim_beh.wdb"/></transform><transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1335914570"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/></transform><transform xil_pn:end_ts="1336089718" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-5756048480961623240" xil_pn:start_ts="1336089718"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/></transform><transform xil_pn:end_ts="1336089718" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7719148281395352834" xil_pn:start_ts="1336089718"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/></transform><transform xil_pn:end_ts="1336089718" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1336089718"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/></transform><transform xil_pn:end_ts="1336089718" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4641019278670948490" xil_pn:start_ts="1336089718"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/></transform><transform xil_pn:end_ts="1336089718" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1336089718"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/></transform><transform xil_pn:end_ts="1336089718" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-2912634102501063032" xil_pn:start_ts="1336089718"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/></transform><transform xil_pn:end_ts="1336515643" xil_pn:in_ck="4673194791943474574" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8986552465892320357" xil_pn:start_ts="1336515631"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="WarningsGenerated"/><status xil_pn:value="ReadyToRun"/><status xil_pn:value="OutOfDateForInputs"/><status xil_pn:value="InputChanged"/><outfile xil_pn:name="INTERCON_P2P.lso"/><outfile xil_pn:name="INTERCON_P2P.ngc"/><outfile xil_pn:name="INTERCON_P2P.ngr"/><outfile xil_pn:name="INTERCON_P2P.prj"/><outfile xil_pn:name="INTERCON_P2P.stx"/><outfile xil_pn:name="INTERCON_P2P.syr"/><outfile xil_pn:name="INTERCON_P2P.xst"/><outfile xil_pn:name="INTERCON_P2P_vhdl.prj"/><outfile xil_pn:name="INTERCON_P2P_xst.xrpt"/><outfile xil_pn:name="SERIALMASTER.ngr"/><outfile xil_pn:name="SYC0001a.ngr"/><outfile xil_pn:name="_xmsgs/xst.xmsgs"/><outfile xil_pn:name="serial_receiver.ngr"/><outfile xil_pn:name="serial_transmitter.ngr"/><outfile xil_pn:name="uart_control.ngr"/><outfile xil_pn:name="uart_wishbone_slave.ngr"/><outfile xil_pn:name="webtalk_pn.xml"/><outfile xil_pn:name="xst"/></transform><transform xil_pn:end_ts="1336084618" xil_pn:in_ck="2653651478373773795" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-7776376010671116565" xil_pn:start_ts="1336084618"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="ReadyToRun"/></transform><transform xil_pn:end_ts="1336513221" xil_pn:in_ck="4758608941402184672" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336513207"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="WarningsGenerated"/><status xil_pn:value="ReadyToRun"/><status xil_pn:value="OutOfDateForInputs"/><status xil_pn:value="OutOfDateForPredecessor"/><status xil_pn:value="OutOfDateForOutputs"/><status xil_pn:value="InputChanged"/><status xil_pn:value="InputRemoved"/><status xil_pn:value="OutputRemoved"/></transform><transform xil_pn:end_ts="1336513228" xil_pn:in_ck="7070038919220904605" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1336513221"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="WarningsGenerated"/><status xil_pn:value="NotReadyToRun"/><status xil_pn:value="OutOfDateForInputs"/><status xil_pn:value="OutOfDateForPredecessor"/><status xil_pn:value="OutOfDateForOutputs"/><status xil_pn:value="InputRemoved"/><status xil_pn:value="OutputChanged"/><status xil_pn:value="OutputRemoved"/></transform><transform xil_pn:end_ts="1336513241" xil_pn:in_ck="5901297062896623158" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1336513228"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="WarningsGenerated"/><status xil_pn:value="NotReadyToRun"/><status xil_pn:value="OutOfDateForInputs"/><status xil_pn:value="OutOfDateForPredecessor"/><status xil_pn:value="OutOfDateForOutputs"/><status xil_pn:value="InputRemoved"/><status xil_pn:value="OutputRemoved"/></transform><transform xil_pn:end_ts="1336513346" xil_pn:in_ck="-1437695683665201866" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1336513333"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="WarningsGenerated"/><status xil_pn:value="NotReadyToRun"/><status xil_pn:value="OutOfDateForInputs"/><status xil_pn:value="OutOfDateForPredecessor"/><status xil_pn:value="OutOfDateForOutputs"/><status xil_pn:value="InputRemoved"/><status xil_pn:value="OutputChanged"/><status xil_pn:value="OutputRemoved"/></transform><transform xil_pn:end_ts="1336249692" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1336249691"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="NotReadyToRun"/><status xil_pn:value="OutOfDateForInputs"/><status xil_pn:value="OutOfDateForPredecessor"/><status xil_pn:value="InputChanged"/><status xil_pn:value="InputRemoved"/></transform><transform xil_pn:end_ts="1336249854" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336249853"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="NotReadyToRun"/><status xil_pn:value="OutOfDateForInputs"/><status xil_pn:value="OutOfDateForPredecessor"/><status xil_pn:value="InputChanged"/><status xil_pn:value="InputRemoved"/></transform><transform xil_pn:end_ts="1336243447" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1336243447"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="NotReadyToRun"/><status xil_pn:value="OutOfDateForInputs"/><status xil_pn:value="OutOfDateForPredecessor"/><status xil_pn:value="InputAdded"/><status xil_pn:value="InputChanged"/><status xil_pn:value="InputRemoved"/></transform><transform xil_pn:end_ts="1336513241" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1336513238"><status xil_pn:value="SuccessfullyRun"/><status xil_pn:value="NotReadyToRun"/><status xil_pn:value="OutOfDateForInputs"/><status xil_pn:value="OutOfDateForPredecessor"/><status xil_pn:value="OutOfDateForOutputs"/><status xil_pn:value="InputRemoved"/><status xil_pn:value="OutputRemoved"/></transform></transforms></generated_project>