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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [iseProject.gise] - Rev 25
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="iseProject.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="baud_generator.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="baud_generator.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="baud_generator.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="baud_generator.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="baud_generator.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="baud_generator.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="baud_generator.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="baud_generator.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="baud_generator_envsettings.html"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="baud_generator_isim_beh.exe"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="baud_generator_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="baud_generator_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="baud_generator_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="divisor.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="divisor.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="divisor.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="divisor.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="divisor.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="divisor.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="divisor.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="divisor.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="divisor_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="divisor_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="divisor_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="divisor_xst.xrpt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="serial_receiver.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="serial_receiver.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="serial_receiver.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="serial_receiver.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="serial_receiver.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="serial_receiver.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="serial_receiver.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="serial_receiver.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="serial_receiver_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="serial_receiver_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="serial_receiver_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="serial_receiver_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="serial_transmitter.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="serial_transmitter.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="serial_transmitter.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="serial_transmitter.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="serial_transmitter.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="serial_transmitter.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="serial_transmitter.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="serial_transmitter.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="serial_transmitter_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="serial_transmitter_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="serial_transmitter_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="serial_transmitter_xst.xrpt"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testBaud_generator_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDivisor_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_receiver_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_transmitter_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_communication_block_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testUart_communication_block_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_control_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testUart_wishbone_slave_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testUart_wishbone_slave_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="uart_communication_blocks.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="uart_communication_blocks.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="uart_communication_blocks.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="uart_communication_blocks.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_communication_blocks.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="uart_communication_blocks.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="uart_communication_blocks.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="uart_communication_blocks.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_communication_blocks_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_communication_blocks_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_communication_blocks_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="uart_communication_blocks_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="uart_control.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="uart_control.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="uart_control.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="uart_control.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_control.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="uart_control.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="uart_control.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="uart_control.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_control_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_control_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_control_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="uart_control_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="uart_wishbone_slave.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="uart_wishbone_slave.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="uart_wishbone_slave.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="uart_wishbone_slave.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_wishbone_slave.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="uart_wishbone_slave.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="uart_wishbone_slave.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="uart_wishbone_slave.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_wishbone_slave_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_wishbone_slave_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_wishbone_slave_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="uart_wishbone_slave_xst.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1335696912" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1335696912">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335914584" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335914584">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="baud_generator.vhd"/>
<outfile xil_pn:name="divisor.vhd"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
<outfile xil_pn:name="serial_receiver.vhd"/>
<outfile xil_pn:name="serial_transmitter.vhd"/>
<outfile xil_pn:name="testBaud_generator.vhd"/>
<outfile xil_pn:name="testDivisor.vhd"/>
<outfile xil_pn:name="testSerial_receiver.vhd"/>
<outfile xil_pn:name="testSerial_transmitter.vhd"/>
<outfile xil_pn:name="testUart_communication_block.vhd"/>
<outfile xil_pn:name="testUart_control.vhd"/>
<outfile xil_pn:name="testUart_wishbone_slave.vhd"/>
<outfile xil_pn:name="uart_communication_blocks.vhd"/>
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_wishbone_slave.vhd"/>
</transform>
<transform xil_pn:end_ts="1335899449" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5308805702929486166" xil_pn:start_ts="1335899449">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335899449" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1238851900205137108" xil_pn:start_ts="1335899449">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335914584" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1430910882053507873" xil_pn:start_ts="1335914584">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335914584" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335914584">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="baud_generator.vhd"/>
<outfile xil_pn:name="divisor.vhd"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
<outfile xil_pn:name="serial_receiver.vhd"/>
<outfile xil_pn:name="serial_transmitter.vhd"/>
<outfile xil_pn:name="testBaud_generator.vhd"/>
<outfile xil_pn:name="testDivisor.vhd"/>
<outfile xil_pn:name="testSerial_receiver.vhd"/>
<outfile xil_pn:name="testSerial_transmitter.vhd"/>
<outfile xil_pn:name="testUart_communication_block.vhd"/>
<outfile xil_pn:name="testUart_control.vhd"/>
<outfile xil_pn:name="testUart_wishbone_slave.vhd"/>
<outfile xil_pn:name="uart_communication_blocks.vhd"/>
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_wishbone_slave.vhd"/>
</transform>
<transform xil_pn:end_ts="1335914587" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8691405173963172662" xil_pn:start_ts="1335914584">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testUart_wishbone_slave_beh.prj"/>
<outfile xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1335914664" xil_pn:in_ck="7043554240611338668" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7109246390254422178" xil_pn:start_ts="1335914664">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1335914570">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1008586360203480345" xil_pn:start_ts="1335914570">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1430910882053507873" xil_pn:start_ts="1335914570">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1335914570">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7853110446436427671" xil_pn:start_ts="1335914570">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1335914570">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="2852686481009242409" xil_pn:start_ts="1335914570">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335914580" xil_pn:in_ck="-2826982315966499730" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8823216100926192740" xil_pn:start_ts="1335914570">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="serial_receiver.ngr"/>
<outfile xil_pn:name="serial_transmitter.ngr"/>
<outfile xil_pn:name="uart_control.ngr"/>
<outfile xil_pn:name="uart_wishbone_slave.lso"/>
<outfile xil_pn:name="uart_wishbone_slave.ngc"/>
<outfile xil_pn:name="uart_wishbone_slave.ngr"/>
<outfile xil_pn:name="uart_wishbone_slave.prj"/>
<outfile xil_pn:name="uart_wishbone_slave.stx"/>
<outfile xil_pn:name="uart_wishbone_slave.syr"/>
<outfile xil_pn:name="uart_wishbone_slave.xst"/>
<outfile xil_pn:name="uart_wishbone_slave_vhdl.prj"/>
<outfile xil_pn:name="uart_wishbone_slave_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
</transforms>
</generated_project>
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