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https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [iseProject.xise] - Rev 24
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"><header><!-- ISE source project file created by Project Navigator. --><!-- --><!-- This file contains project source information including a list of --><!-- project source files, project and process properties. This file, --><!-- along with the project source files, is sufficient to open and --><!-- implement in ISE Project Navigator. --><!-- --><!-- Copyright (c) 1995-2011 Xilinx, Inc. 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xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Output File Name" xil_pn:value="uart_wishbone_slave" xil_pn:valueState="default"/><property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/><property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/><property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/><property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/><property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/><property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/><property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="uart_wishbone_slave_map.vhd" xil_pn:valueState="default"/><property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="uart_wishbone_slave_timesim.vhd" xil_pn:valueState="default"/><property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="uart_wishbone_slave_synthesis.vhd" xil_pn:valueState="default"/><property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="uart_wishbone_slave_translate.vhd" xil_pn:valueState="default"/><property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/><property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/><property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/><property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/><property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/><property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/><property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/><property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/><property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/><property xil_pn:name="Rename Top Level Entity to" xil_pn:value="uart_wishbone_slave" xil_pn:valueState="default"/><property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/><property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/><property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/><property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/><property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/><property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/><property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/><property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/><property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/><property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/><property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testUart_wishbone_slave" xil_pn:valueState="non-default"/><property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="non-default"/><property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/><property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/><property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ms" xil_pn:valueState="non-default"/><property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/><property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/><property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/><property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/><property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/><property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="default"/><property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/><property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/><property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/><property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/><property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/><property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/><property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/><property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/><property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/><property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/><property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/><property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/><property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/><property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/><property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/><property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/><property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/><property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/><property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/><property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/><property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/><property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/><!-- --><!-- The following properties are for internal use only. These should not be modified.--><!-- --><property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testUart_wishbone_slave|behavior" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/><property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/><property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-04-20T22:53:04" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="225093D1BA50465FB2D0D99DBD16A3DC" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/></properties><bindings/><libraries/><autoManagedFiles><!-- The following files are identified by `include statements in verilog --><!-- source files and are automatically managed by Project Navigator. --><!-- --><!-- Do not hand-edit this section, as it will be overwritten when the --><!-- project is analyzed based on files automatically identified as --><!-- include files. --></autoManagedFiles></project>
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