Subversion Repositories uart_block

ISim log file
Running: E:\uart_block\hdl\iseProject\testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb 
ISim O.87xd (signature 0xc3576ebc)
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This is a Full version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testUart_wishbone_slave.vhd:stim_proc 
 
INFO: Simulator is stopped.