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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [isim.log] - Rev 40

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ISim log file
Running: E:\uart_block\hdl\iseProject\testUart_communication_block_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.wdb 
ISim O.87xd (signature 0xc3576ebc)
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WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.


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This is a Full version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.

** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testUart_communication_block.vhd:stim_proc 
 
INFO: Simulator is stopped.

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