Subversion Repositories uart_block

Release 13.4 - xst O.87xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> 
Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
 
--> 
Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
 
--> 
Reading design: serial_receiver.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "serial_receiver.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "serial_receiver"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320

---- Source Options
Top Module Name                    : serial_receiver
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.
Architecture pkgdefinitions of Entity pkgdefinitions is up to date.
Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" in Library work.
Architecture behavioral of Entity serial_receiver is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <serial_receiver> in library <work> (architecture <behavioral>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <serial_receiver> in library <work> (Architecture <behavioral>).
Entity <serial_receiver> analyzed. Unit <serial_receiver> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <serial_receiver>.
    Related source file is "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd".
    Found finite state machine <FSM_0> for signal <current_s>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 10                                             |
    | Inputs             | 0                                              |
    | Outputs            | 11                                             |
    | Clock              | baudClk                   (rising_edge)        |
    | Reset              | syncDetected              (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | bit0                                           |
    | Power Up State     | bit0                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <filterRx>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 8                                              |
    | Inputs             | 2                                              |
    | Outputs            | 4                                              |
    | Clock              | baudOverSampleClk         (rising_edge)        |
    | Reset              | rst                       (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | s0                                             |
    | Power Up State     | s0                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <data_ready>.
    Found 8-bit register for signal <data_byte>.
    Found 8-bit register for signal <byteReceived>.
    Found 1-bit register for signal <syncDetected>.
    Summary:
        inferred   2 Finite State Machine(s).
        inferred  18 D-type flip-flop(s).
Unit <serial_receiver> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 11
 1-bit register                                        : 10
 8-bit register                                        : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <filterRx/FSM> on signal <filterRx[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 s0    | 00
 s1    | 01
 s2    | 11
 s3    | 10
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <current_s/FSM> on signal <current_s[1:10]> with one-hot encoding.
-----------------------
 State   | Encoding
-----------------------
 bit0    | 0000000001
 bit1    | 0000000010
 bit2    | 0000000100
 bit3    | 0000001000
 bit4    | 0000010000
 bit5    | 0000100000
 bit6    | 0001000000
 bit7    | 0010000000
 rx_stop | 0100000000
 rx_idle | 1000000000
-----------------------

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 2
# Registers                                            : 18
 Flip-Flops                                            : 18

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:2261 - The FF/Latch <current_s_FSM_FFd1> in Unit <serial_receiver> is equivalent to the following FF/Latch, which will be removed : <data_ready> 

Optimizing unit <serial_receiver> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block serial_receiver, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 29
 Flip-Flops                                            : 29

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : serial_receiver.ngr
Top Level Output File Name         : serial_receiver
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 13

Cell Usage :
# BELS                             : 19
#      GND                         : 1
#      INV                         : 1
#      LUT2                        : 1
#      LUT2_L                      : 1
#      LUT3                        : 1
#      LUT3_D                      : 1
#      LUT4                        : 11
#      LUT4_D                      : 1
#      VCC                         : 1
# FlipFlops/Latches                : 29
#      FDC                         : 11
#      FDCE                        : 9
#      FDE                         : 8
#      FDP                         : 1
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 11
#      IBUF                        : 2
#      OBUF                        : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s500efg320-4 

 Number of Slices:                       19  out of   4656     0%  
 Number of Slice Flip Flops:             29  out of   9312     0%  
 Number of 4 input LUTs:                 17  out of   9312     0%  
 Number of IOs:                          13
 Number of bonded IOBs:                  13  out of    232     5%  
 Number of GCLKs:                         2  out of     24     8%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
baudOverSampleClk                  | BUFGP                  | 3     |
baudClk                            | BUFGP                  | 26    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
---------------------------------------------------------------+------------------------+-------+
Control Signal                                                 | Buffer(FF name)        | Load  |
---------------------------------------------------------------+------------------------+-------+
current_s_FSM_Acst_FSM_inv(current_s_FSM_Acst_FSM_inv1_INV_0:O)| NONE(byteReceived_0)   | 18    |
rst                                                            | IBUF                   | 3     |
---------------------------------------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 4.853ns (Maximum Frequency: 206.058MHz)
   Minimum input arrival time before clock: 4.569ns
   Maximum output required time after clock: 4.450ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'baudOverSampleClk'
  Clock period: 2.489ns (frequency: 401.768MHz)
  Total number of paths / destination ports: 6 / 3
-------------------------------------------------------------------------
Delay:               2.489ns (Levels of Logic = 1)
  Source:            syncDetected (FF)
  Destination:       syncDetected (FF)
  Source Clock:      baudOverSampleClk rising
  Destination Clock: baudOverSampleClk rising

  Data Path: syncDetected to syncDetected
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             10   0.591   0.886  syncDetected (syncDetected)
     LUT4:I3->O            1   0.704   0.000  syncDetected_mux00001 (syncDetected_mux0000)
     FDC:D                     0.308          syncDetected
    ----------------------------------------
    Total                      2.489ns (1.603ns logic, 0.886ns route)
                                       (64.4% logic, 35.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'baudClk'
  Clock period: 4.853ns (frequency: 206.058MHz)
  Total number of paths / destination ports: 113 / 25
-------------------------------------------------------------------------
Delay:               4.853ns (Levels of Logic = 3)
  Source:            current_s_FSM_FFd7 (FF)
  Destination:       data_byte_0 (FF)
  Source Clock:      baudClk rising
  Destination Clock: baudClk rising

  Data Path: current_s_FSM_FFd7 to data_byte_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.591   0.706  current_s_FSM_FFd7 (current_s_FSM_FFd7)
     LUT4:I0->O            1   0.704   0.424  data_byte_mux0000<0>1_SW0 (N5)
     LUT4_D:I3->O          7   0.704   0.712  data_byte_mux0000<0>1 (N01)
     LUT4:I3->O            1   0.704   0.000  data_byte_mux0000<6>1 (data_byte_mux0000<6>)
     FDE:D                     0.308          data_byte_6
    ----------------------------------------
    Total                      4.853ns (3.011ns logic, 1.842ns route)
                                       (62.0% logic, 38.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'baudOverSampleClk'
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset:              3.366ns (Levels of Logic = 2)
  Source:            serial_in (PAD)
  Destination:       filterRx_FSM_FFd2 (FF)
  Destination Clock: baudOverSampleClk rising

  Data Path: serial_in to filterRx_FSM_FFd2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            12   1.218   1.136  serial_in_IBUF (serial_in_IBUF)
     LUT2:I0->O            1   0.704   0.000  filterRx_FSM_FFd2-In1 (filterRx_FSM_FFd2-In)
     FDC:D                     0.308          filterRx_FSM_FFd2
    ----------------------------------------
    Total                      3.366ns (2.230ns logic, 1.136ns route)
                                       (66.3% logic, 33.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'baudClk'
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Offset:              4.569ns (Levels of Logic = 3)
  Source:            serial_in (PAD)
  Destination:       data_byte_7 (FF)
  Destination Clock: baudClk rising

  Data Path: serial_in to data_byte_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            12   1.218   1.136  serial_in_IBUF (serial_in_IBUF)
     LUT4:I0->O            1   0.704   0.499  data_byte_mux0000<7>_SW0 (N3)
     LUT3:I1->O            1   0.704   0.000  data_byte_mux0000<7> (data_byte_mux0000<7>)
     FDE:D                     0.308          data_byte_7
    ----------------------------------------
    Total                      4.569ns (2.934ns logic, 1.635ns route)
                                       (64.2% logic, 35.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'baudClk'
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Offset:              4.450ns (Levels of Logic = 1)
  Source:            current_s_FSM_FFd1 (FF)
  Destination:       data_ready (PAD)
  Source Clock:      baudClk rising

  Data Path: current_s_FSM_FFd1 to data_ready
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             4   0.591   0.587  current_s_FSM_FFd1 (current_s_FSM_FFd1)
     OBUF:I->O                 3.272          data_ready_OBUF (data_ready)
    ----------------------------------------
    Total                      4.450ns (3.863ns logic, 0.587ns route)
                                       (86.8% logic, 13.2% route)

=========================================================================


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.59 secs
 
--> 


Total memory usage is 164420 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)