Subversion Repositories uart_block

Release 13.4 - xst O.87xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> 
Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
 
--> 
Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
 
--> 
Reading design: serial_transmitter.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "serial_transmitter.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "serial_transmitter"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320

---- Source Options
Top Module Name                    : serial_transmitter
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.
Architecture pkgdefinitions of Entity pkgdefinitions is up to date.
Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" in Library work.
Architecture behavioral of Entity serial_transmitter is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <serial_transmitter> in library <work> (architecture <behavioral>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <serial_transmitter> in library <work> (Architecture <behavioral>).
Entity <serial_transmitter> analyzed. Unit <serial_transmitter> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <serial_transmitter>.
    Related source file is "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd".
    Found finite state machine <FSM_0> for signal <current_s>.
    -----------------------------------------------------------------------
    | States             | 12                                             |
    | Transitions        | 12                                             |
    | Inputs             | 0                                              |
    | Outputs            | 13                                             |
    | Clock              | baudClk                   (rising_edge)        |
    | Reset              | rst                       (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | tx_idle                                        |
    | Power Up State     | tx_idle                                        |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
        inferred   1 Finite State Machine(s).
Unit <serial_transmitter> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <current_s/FSM> on signal <current_s[1:12]> with one-hot encoding.
--------------------------
 State    | Encoding
--------------------------
 tx_idle  | 000000000001
 tx_start | 000000000010
 bit0     | 000000000100
 bit1     | 000000001000
 bit2     | 000000010000
 bit3     | 000000100000
 bit4     | 000001000000
 bit5     | 000010000000
 bit6     | 000100000000
 bit7     | 001000000000
 tx_stop1 | 010000000000
 tx_stop2 | 100000000000
--------------------------

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <serial_transmitter> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block serial_transmitter, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 12
 Flip-Flops                                            : 12

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : serial_transmitter.ngr
Top Level Output File Name         : serial_transmitter
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 12

Cell Usage :
# BELS                             : 9
#      GND                         : 1
#      LUT2                        : 1
#      LUT4                        : 6
#      VCC                         : 1
# FlipFlops/Latches                : 12
#      FDC                         : 10
#      FDCE                        : 1
#      FDP                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 11
#      IBUF                        : 9
#      OBUF                        : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s500efg320-4 

 Number of Slices:                        7  out of   4656     0%  
 Number of Slice Flip Flops:             12  out of   9312     0%  
 Number of 4 input LUTs:                  7  out of   9312     0%  
 Number of IOs:                          12
 Number of bonded IOBs:                  12  out of    232     5%  
 Number of GCLKs:                         1  out of     24     4%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
baudClk                            | BUFGP                  | 12    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
rst                                | IBUF                   | 12    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 1.677ns (Maximum Frequency: 596.303MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 8.036ns
   Maximum combinational path delay: 8.540ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'baudClk'
  Clock period: 1.677ns (frequency: 596.303MHz)
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Delay:               1.677ns (Levels of Logic = 0)
  Source:            current_s_FSM_FFd2 (FF)
  Destination:       current_s_FSM_FFd1 (FF)
  Source Clock:      baudClk rising
  Destination Clock: baudClk rising

  Data Path: current_s_FSM_FFd2 to current_s_FSM_FFd1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.591   0.531  current_s_FSM_FFd2 (current_s_FSM_FFd2)
     FDCE:CE                   0.555          current_s_FSM_FFd1
    ----------------------------------------
    Total                      1.677ns (1.146ns logic, 0.531ns route)
                                       (68.3% logic, 31.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'baudClk'
  Total number of paths / destination ports: 13 / 2
-------------------------------------------------------------------------
Offset:              8.036ns (Levels of Logic = 4)
  Source:            current_s_FSM_FFd7 (FF)
  Destination:       serial_out (PAD)
  Source Clock:      baudClk rising

  Data Path: current_s_FSM_FFd7 to serial_out
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.591   0.622  current_s_FSM_FFd7 (current_s_FSM_FFd7)
     LUT4:I0->O            1   0.704   0.595  serial_out12 (serial_out12)
     LUT4:I0->O            1   0.704   0.424  serial_out48_SW0 (N01)
     LUT4:I3->O            1   0.704   0.420  serial_out48 (serial_out_OBUF)
     OBUF:I->O                 3.272          serial_out_OBUF (serial_out)
    ----------------------------------------
    Total                      8.036ns (5.975ns logic, 2.061ns route)
                                       (74.4% logic, 25.6% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 8 / 1
-------------------------------------------------------------------------
Delay:               8.540ns (Levels of Logic = 5)
  Source:            data_byte<3> (PAD)
  Destination:       serial_out (PAD)

  Data Path: data_byte<3> to serial_out
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.218   0.499  data_byte_3_IBUF (data_byte_3_IBUF)
     LUT4:I1->O            1   0.704   0.595  serial_out12 (serial_out12)
     LUT4:I0->O            1   0.704   0.424  serial_out48_SW0 (N01)
     LUT4:I3->O            1   0.704   0.420  serial_out48 (serial_out_OBUF)
     OBUF:I->O                 3.272          serial_out_OBUF (serial_out)
    ----------------------------------------
    Total                      8.540ns (6.602ns logic, 1.938ns route)
                                       (77.3% logic, 22.7% route)

=========================================================================


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.47 secs
 
--> 


Total memory usage is 163788 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)