Subversion Repositories uart_fpga_slow_control_migrated

<b>Control the activity and status of your FPGA by targeting a memory mapped space inside it.</b>

<p>
<br />Based on:
<br />
<ul>
<li>-- elements from the GH libraries (<a href="http://opencores.org/project,gh_vhdl_library">gh_library</a>)</li>
<li>-- HLeFevre UART project (<a href="http://opencores.org/project,a_vhd_16550_uart">LeFevre_uart</a>)</li>
</ul>
<br />Simple three steps access procedure:
<ul>
<li>-- Write words of 2 bytes address and 4 bytes data.</li>
<li>-- Ask for an update targeting the update register (default 0x8000 0x00000000)</li>
<li>-- Read words of 2 bytes address and 4 bytes data.</li>
</ul>
<br />The code comes plug and play:
<ul>
<li>* the whole uart initialization process is automatic</li>
<li>* 4 pins interface to the outsideworld: serial tx, serial rx, uart clock, hard reset</li>
<li>* up to 2^16 32 bit wide registers for user logic control and monitor</li>
</ul>

<br />Declare the registers you want to read and write in the top level entity: 
<ul>
<li>+ the rest will be handled automatically by FSMs.</li>
<li>+ almost no documentation is required.</li>
<li>+ no knowledge of the internals of the core required.</li>
<li>+ the top entity is self-explanatory.</li>
</ul>

<br />Remotely control the logic from a PC:
<ul>
<li>~ Under Windows use RealTerm to simply send and receive HEX commands ( http://realterm.sourceforge.net/ ).</li>
<li>~ Simple Python script to drive the uart via command line in linux (see software details tab above).</li>
<li>~ TCP/IP to UART bridging is just around the corner using inexpensive external devices.</li>
</ul>

<br />crossplatform compatible (tested on Xilinx Virtex-5 and Altera Stratix-4 devices). 
<br />Tested up to 1 Mbps with a 29.4912 MHz oscillator.

<br />
<br /><b>## Feeback:</b>
<br />Give comments and feedback using the official core thread on the OpenCores forum:
<br /><a href="http://opencores.org/forum,Cores,0,4443">forum_thread</a>
</p>