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Subversion Repositories uart_plb
[/] [uart_plb/] [trunk/] [firmware/] [platform/] [system.xml] - Rev 3
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<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Fri Jun 03 18:05:35 2011"><SYSTEMINFO ARCH="spartan3e" DEVICE="xc3s1600e" PACKAGE="fg320" PART="xc3s1600efg320-4" SOURCE="C:/uart_plb/system.xmp" SPEEDGRADE="-4"/><EXTERNALPORTS><PORT DIR="I" MHS_INDEX="0" NAME="fpga_0_RS232_DCE_RX_pin" SIGNAME="fpga_0_RS232_DCE_RX_pin"/><PORT DIR="O" MHS_INDEX="1" NAME="fpga_0_RS232_DCE_TX_pin" SIGNAME="fpga_0_RS232_DCE_TX_pin"/><PORT CLKFREQUENCY="50000000" DIR="I" MHS_INDEX="2" NAME="fpga_0_clk_1_sys_clk_pin" SIGIS="CLK" SIGNAME="CLK_S"/><PORT DIR="I" MHS_INDEX="3" NAME="fpga_0_rst_1_sys_rst_pin" RSTPOLARITY="1" SIGIS="RST" SIGNAME="sys_rst_s"/><PORT DIR="O" MHS_INDEX="4" NAME="uart_plb_0_tx_sout_pin" SIGNAME="uart_plb_0_tx_sout"/><PORT DIR="I" MHS_INDEX="5" NAME="uart_plb_0_rx_sin_pin" SIGNAME="uart_plb_0_rx_sin"/></EXTERNALPORTS><MODULES><MODULE HWVERSION="8.10.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="0" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE"><DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION><DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_10_a/doc/microblaze.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="50000000"/><PARAMETER MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan3e"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/><PARAMETER MPD_INDEX="6" NAME="C_FAULT_TOLERANT" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Fault Tolerance Support</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="7" NAME="C_ECC_USE_CE_EXCEPTION" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="8" NAME="C_ENDIANNESS" TYPE="integer" VALUE="0"/><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="9" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="1"><DESCRIPTION>Select implementation to optimize area (with lower instruction throughput)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="10" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="11" NAME="C_INTERCONNECT" TYPE="integer" VALUE="1"><DESCRIPTION>Select Bus Interfaces</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="12" NAME="C_STREAM_INTERCONNECT" TYPE="integer" VALUE="0"><DESCRIPTION>Select Stream Interfaces</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="13" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="14" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="15" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="16" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="17" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="18" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="19" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="20" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="21" NAME="C_M_AXI_DP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="22" NAME="C_M_AXI_DP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="23" NAME="C_M_AXI_DP_SUPPORTS_READ" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="24" NAME="C_M_AXI_DP_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="25" NAME="C_M_AXI_DP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="26" NAME="C_M_AXI_DP_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="27" NAME="C_M_AXI_DP_ADDR_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="28" NAME="C_M_AXI_DP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/><PARAMETER MPD_INDEX="29" NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="30" NAME="C_INTERCONNECT_M_AXI_DP_READ_ISSUING" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="31" NAME="C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="32" NAME="C_M_AXI_IP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="33" NAME="C_M_AXI_IP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="34" NAME="C_M_AXI_IP_SUPPORTS_READ" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="35" NAME="C_M_AXI_IP_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="36" NAME="C_M_AXI_IP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="37" NAME="C_M_AXI_IP_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="38" NAME="C_M_AXI_IP_ADDR_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="39" NAME="C_M_AXI_IP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/><PARAMETER MPD_INDEX="40" NAME="C_INTERCONNECT_M_AXI_IP_READ_ISSUING" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="41" NAME="C_D_AXI" TYPE="integer" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="42" NAME="C_D_PLB" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="43" NAME="C_D_LMB" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="44" NAME="C_I_AXI" TYPE="integer" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="45" NAME="C_I_PLB" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="46" NAME="C_I_LMB" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="47" NAME="C_USE_MSR_INSTR" TYPE="integer" VALUE="1"><DESCRIPTION>Enable Additional Machine Status Register Instructions</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="48" NAME="C_USE_PCMP_INSTR" TYPE="integer" VALUE="1"><DESCRIPTION>Enable Pattern Comparator</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="49" NAME="C_USE_BARREL" TYPE="integer" VALUE="1"><DESCRIPTION>Enable Barrel Shifter</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="50" NAME="C_USE_DIV" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Integer Divider</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="51" NAME="C_USE_HW_MUL" TYPE="integer" VALUE="1"><DESCRIPTION>Enable Integer Multiplier</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="52" NAME="C_USE_FPU" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Floating Point Unit</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="53" NAME="C_UNALIGNED_EXCEPTIONS" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Unaligned Data Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="54" NAME="C_ILL_OPCODE_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Illegal Instruction Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="55" NAME="C_M_AXI_I_BUS_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Instruction-side AXI Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="56" NAME="C_M_AXI_D_BUS_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Data-side AXI Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="57" NAME="C_IPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Instruction-side PLB Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="58" NAME="C_DPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Data-side PLB Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="59" NAME="C_DIV_ZERO_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Integer Divide Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="60" NAME="C_FPU_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Floating Point Unit Exceptions</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="61" NAME="C_FSL_EXCEPTION" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Stream Exception</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="62" NAME="C_USE_STACK_PROTECTION" TYPE="integer" VALUE="0"><DESCRIPTION><qt>Enable stack protection</qt></DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="63" NAME="C_PVR" TYPE="integer" VALUE="0"><DESCRIPTION>Specifies Processor Version Register</DESCRIPTION></PARAMETER><PARAMETER ENDIAN="BIG" LSB="7" MPD_INDEX="64" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00"><DESCRIPTION>Specify USER1 Bits in Processor Version Register</DESCRIPTION></PARAMETER><PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="65" MSB="0" NAME="C_PVR_USER2" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>Specify USER2 Bits in Processor Version Registers</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="66" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1"><DESCRIPTION>Enable MicroBlaze Debug Module Interface</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="67" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="1"><DESCRIPTION>Number of PC Breakpoints </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="68" NAME="C_NUMBER_OF_RD_ADDR_BRK" TYPE="integer" VALUE="0"><DESCRIPTION>Number of Read Address Watchpoints </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="69" NAME="C_NUMBER_OF_WR_ADDR_BRK" TYPE="integer" VALUE="0"><DESCRIPTION>Number of Write Address Watchpoints </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="70" NAME="C_INTERRUPT_IS_EDGE" TYPE="integer" VALUE="0"><DESCRIPTION>Sense Interrupt on Edge vs. Level </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="71" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1"><DESCRIPTION>Sense Interrupt on Rising vs. Falling Edge </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="72" NAME="C_RESET_MSR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>Specify Reset Value for Select MSR Bits</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="73" NAME="C_OPCODE_0x0_ILLEGAL" TYPE="integer" VALUE="0"><DESCRIPTION><qt>Generate Illegal Instruction Exception for NULL Instruction</qt></DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="74" NAME="C_FSL_LINKS" TYPE="integer" VALUE="0"><DESCRIPTION>Number of Stream Links </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="75" NAME="C_FSL_DATA_SIZE" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="76" NAME="C_USE_EXTENDED_FSL_INSTR" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Additional Stream Instructions</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="77" NAME="C_M0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="78" NAME="C_S0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="79" NAME="C_M1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="80" NAME="C_S1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="81" NAME="C_M2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="82" NAME="C_S2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="83" NAME="C_M3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="84" NAME="C_S3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="85" NAME="C_M4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="86" NAME="C_S4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="87" NAME="C_M5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="88" NAME="C_S5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="89" NAME="C_M6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="90" NAME="C_S6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="91" NAME="C_M7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="92" NAME="C_S7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="93" NAME="C_M8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="94" NAME="C_S8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="95" NAME="C_M9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="96" NAME="C_S9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="97" NAME="C_M10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="98" NAME="C_S10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="99" NAME="C_M11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="100" NAME="C_S11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="101" NAME="C_M12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="102" NAME="C_S12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="103" NAME="C_M13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="104" NAME="C_S13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="105" NAME="C_M14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="106" NAME="C_S14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="107" NAME="C_M15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="108" NAME="C_S15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/><PARAMETER MPD_INDEX="109" NAME="C_M0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="110" NAME="C_S0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="111" NAME="C_M1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="112" NAME="C_S1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="113" NAME="C_M2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="114" NAME="C_S2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="115" NAME="C_M3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="116" NAME="C_S3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="117" NAME="C_M4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="118" NAME="C_S4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="119" NAME="C_M5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="120" NAME="C_S5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="121" NAME="C_M6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="122" NAME="C_S6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="123" NAME="C_M7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="124" NAME="C_S7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="125" NAME="C_M8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="126" NAME="C_S8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="127" NAME="C_M9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="128" NAME="C_S9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="129" NAME="C_M10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="130" NAME="C_S10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="131" NAME="C_M11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="132" NAME="C_S11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="133" NAME="C_M12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="134" NAME="C_S12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="135" NAME="C_M13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="136" NAME="C_S13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="137" NAME="C_M14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="138" NAME="C_S14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="139" NAME="C_M15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="140" NAME="C_S15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER ADDRESS="NONE" MPD_INDEX="141" NAME="C_ICACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>I-Cache Base Address </DESCRIPTION></PARAMETER><PARAMETER ADDRESS="NONE" MPD_INDEX="142" NAME="C_ICACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0x3FFFFFFF"><DESCRIPTION>I-Cache High Address </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="143" NAME="C_USE_ICACHE" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Instruction Cache </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="144" NAME="C_ALLOW_ICACHE_WR" TYPE="integer" VALUE="1"><DESCRIPTION>Enable I-Cache Writes</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="145" NAME="C_ADDR_TAG_BITS" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="146" NAME="C_CACHE_BYTE_SIZE" TYPE="integer" VALUE="8192"><DESCRIPTION>Size of the I-Cache in Bytes</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="147" NAME="C_ICACHE_USE_FSL" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="148" NAME="C_ICACHE_LINE_LEN" TYPE="integer" VALUE="4"><DESCRIPTION>Instruction Cache Line Length</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="149" NAME="C_ICACHE_ALWAYS_USED" TYPE="integer" VALUE="0"><DESCRIPTION>Use Cache Links for All I-Cache Memory Accesses </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="150" NAME="C_ICACHE_INTERFACE" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="151" NAME="C_ICACHE_VICTIMS" TYPE="integer" VALUE="0"><DESCRIPTION>Number of I-Cache Victims</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="152" NAME="C_ICACHE_STREAMS" TYPE="integer" VALUE="0"><DESCRIPTION>Number of I-Cache Streams</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="153" NAME="C_ICACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0"><DESCRIPTION>Use Distributed RAM for I-Cache Tags</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="154" NAME="C_ICACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="155" NAME="C_M_AXI_IC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="156" NAME="C_M_AXI_IC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="157" NAME="C_M_AXI_IC_SUPPORTS_READ" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="158" NAME="C_M_AXI_IC_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="159" NAME="C_M_AXI_IC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="160" NAME="C_M_AXI_IC_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="161" NAME="C_M_AXI_IC_ADDR_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="162" NAME="C_M_AXI_IC_PROTOCOL" TYPE="string" VALUE="AXI4"/><PARAMETER MPD_INDEX="163" NAME="C_M_AXI_IC_USER_VALUE" TYPE="integer" VALUE="0b11111"/><PARAMETER MPD_INDEX="164" NAME="C_M_AXI_IC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="165" NAME="C_M_AXI_IC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/><PARAMETER MPD_INDEX="166" NAME="C_M_AXI_IC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/><PARAMETER MPD_INDEX="167" NAME="C_M_AXI_IC_WUSER_WIDTH" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="168" NAME="C_M_AXI_IC_RUSER_WIDTH" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="169" NAME="C_M_AXI_IC_BUSER_WIDTH" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="170" NAME="C_INTERCONNECT_M_AXI_IC_READ_ISSUING" TYPE="integer" VALUE="2"/><PARAMETER ADDRESS="NONE" MPD_INDEX="171" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>D-Cache Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="NONE" MPD_INDEX="172" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0x3FFFFFFF"><DESCRIPTION>D-Cache High Address</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="173" NAME="C_USE_DCACHE" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Data Cache</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="174" NAME="C_ALLOW_DCACHE_WR" TYPE="integer" VALUE="1"><DESCRIPTION>Enable D-Cache Writes</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="175" NAME="C_DCACHE_ADDR_TAG" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="176" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="8192"><DESCRIPTION>Size of D-Cache in Bytes</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="177" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="178" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="4"><DESCRIPTION>Data Cache Line Length</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="179" NAME="C_DCACHE_ALWAYS_USED" TYPE="integer" VALUE="0"><DESCRIPTION>Use Cache Links for All D-Cache Memory Accesses </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="180" NAME="C_DCACHE_INTERFACE" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="181" NAME="C_DCACHE_USE_WRITEBACK" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Write-back Storage Policy</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="182" NAME="C_DCACHE_VICTIMS" TYPE="integer" VALUE="0"><DESCRIPTION>Number of D-Cache Victims</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="183" NAME="C_DCACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0"><DESCRIPTION>Use Distributed RAM for D-Cache Tags</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="184" NAME="C_DCACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="185" NAME="C_M_AXI_DC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="186" NAME="C_M_AXI_DC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="187" NAME="C_M_AXI_DC_SUPPORTS_READ" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="188" NAME="C_M_AXI_DC_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="189" NAME="C_M_AXI_DC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="190" NAME="C_M_AXI_DC_DATA_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="191" NAME="C_M_AXI_DC_ADDR_WIDTH" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="192" NAME="C_M_AXI_DC_PROTOCOL" TYPE="string" VALUE="AXI4"/><PARAMETER MPD_INDEX="193" NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/><PARAMETER MPD_INDEX="194" NAME="C_M_AXI_DC_USER_VALUE" TYPE="integer" VALUE="0b11111"/><PARAMETER MPD_INDEX="195" NAME="C_M_AXI_DC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="196" NAME="C_M_AXI_DC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/><PARAMETER MPD_INDEX="197" NAME="C_M_AXI_DC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/><PARAMETER MPD_INDEX="198" NAME="C_M_AXI_DC_WUSER_WIDTH" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="199" NAME="C_M_AXI_DC_RUSER_WIDTH" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="200" NAME="C_M_AXI_DC_BUSER_WIDTH" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="201" NAME="C_INTERCONNECT_M_AXI_DC_READ_ISSUING" TYPE="integer" VALUE="2"/><PARAMETER MPD_INDEX="202" NAME="C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING" TYPE="integer" VALUE="32"/><PARAMETER MPD_INDEX="203" NAME="C_USE_MMU" TYPE="integer" VALUE="0"><DESCRIPTION>Memory Management</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="204" NAME="C_MMU_DTLB_SIZE" TYPE="integer" VALUE="4"><DESCRIPTION>Data Shadow Translation Look-Aside Buffer Size</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="205" NAME="C_MMU_ITLB_SIZE" TYPE="integer" VALUE="2"><DESCRIPTION>Instruction Shadow Translation Look-Aside Buffer Size</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="206" NAME="C_MMU_TLB_ACCESS" TYPE="integer" VALUE="3"><DESCRIPTION>Enable Access to Memory Management Special Registers</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="207" NAME="C_MMU_ZONES" TYPE="integer" VALUE="16"><DESCRIPTION>Number of Memory Protection Zones</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="208" NAME="C_MMU_PRIVILEGED_INSTR" TYPE="integer" VALUE="0"><DESCRIPTION>Privileged Instructions</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="209" NAME="C_USE_INTERRUPT" TYPE="integer" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="210" NAME="C_USE_EXT_BRK" TYPE="integer" VALUE="1"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="211" NAME="C_USE_EXT_NM_BRK" TYPE="integer" VALUE="1"/><PARAMETER MPD_INDEX="212" NAME="C_USE_BRANCH_TARGET_CACHE" TYPE="integer" VALUE="0"><DESCRIPTION>Enable Branch Target Cache</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="213" NAME="C_BRANCH_TARGET_CACHE_SIZE" TYPE="integer" VALUE="0"><DESCRIPTION>Branch Target Cache Size</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="MB_RESET" SIGIS="RST" SIGNAME="mb_reset"/><PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="3" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="microblaze_0_Interrupt"/><PORT BUS="DPLB:IPLB:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/><PORT BUS="DLMB:ILMB" DEF_SIGNAME="dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="RESET" SIGIS="RST" SIGNAME="dlmb_LMB_Rst"/><PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_BRK" SIGNAME="Ext_BRK"/><PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="5" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK"/><PORT DIR="I" MPD_INDEX="6" NAME="DBG_STOP" SIGNAME="__NOC__"/><PORT DIR="O" MPD_INDEX="7" NAME="MB_Halted" SIGNAME="__NOC__"/><PORT DIR="O" MPD_INDEX="8" NAME="MB_Error" SIGNAME="__NOC__"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="INSTR" RIGHT="31" SIGNAME="ilmb_LMB_ReadDBus" VECFORMULA="[0:31]"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_Ready" DIR="I" MPD_INDEX="10" NAME="IREADY" SIGNAME="ilmb_LMB_Ready"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_Wait" DIR="I" MPD_INDEX="11" NAME="IWAIT" SIGNAME="ilmb_LMB_Wait"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_CE" DIR="I" MPD_INDEX="12" NAME="ICE" SIGNAME="ilmb_LMB_CE"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_UE" DIR="I" MPD_INDEX="13" NAME="IUE" SIGNAME="ilmb_LMB_UE"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="INSTR_ADDR" RIGHT="31" SIGNAME="ilmb_M_ABus" VECFORMULA="[0:31]"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="IFETCH" SIGNAME="ilmb_M_ReadStrobe"/><PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_AddrStrobe" DIR="O" MPD_INDEX="16" NAME="I_AS" SIGNAME="ilmb_M_AddrStrobe"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_ABort" DIR="O" MPD_INDEX="17" NAME="IPLB_M_ABort" SIGNAME="mb_plb_M_ABort"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="IPLB_M_ABus" RIGHT="31" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:31]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="IPLB_M_UABus" RIGHT="31" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:31]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="20" MSB="0" NAME="IPLB_M_BE" RIGHT="3" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:(C_IPLB_DWIDTH-1)/8]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_busLock" DIR="O" MPD_INDEX="21" NAME="IPLB_M_busLock" SIGNAME="mb_plb_M_busLock"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_lockErr" DIR="O" MPD_INDEX="22" NAME="IPLB_M_lockErr" SIGNAME="mb_plb_M_lockErr"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="IPLB_M_MSize" RIGHT="1" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:1]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_priority" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="IPLB_M_priority" RIGHT="1" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:1]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_rdBurst" DIR="O" MPD_INDEX="25" NAME="IPLB_M_rdBurst" SIGNAME="mb_plb_M_rdBurst"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_request" DIR="O" MPD_INDEX="26" NAME="IPLB_M_request" SIGNAME="mb_plb_M_request"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_RNW" DIR="O" MPD_INDEX="27" NAME="IPLB_M_RNW" SIGNAME="mb_plb_M_RNW"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="28" MSB="0" NAME="IPLB_M_size" RIGHT="3" SIGNAME="mb_plb_M_size" VECFORMULA="[0:3]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="IPLB_M_TAttribute" RIGHT="15" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:15]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="30" MSB="0" NAME="IPLB_M_type" RIGHT="2" SIGNAME="mb_plb_M_type" VECFORMULA="[0:2]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_wrBurst" DIR="O" MPD_INDEX="31" NAME="IPLB_M_wrBurst" SIGNAME="mb_plb_M_wrBurst"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="IPLB_M_wrDBus" RIGHT="31" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="I" MPD_INDEX="33" NAME="IPLB_MBusy" SIGNAME="mb_plb_PLB_MBusy"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="I" MPD_INDEX="34" NAME="IPLB_MRdErr" SIGNAME="mb_plb_PLB_MRdErr"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="I" MPD_INDEX="35" NAME="IPLB_MWrErr" SIGNAME="mb_plb_PLB_MWrErr"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="I" MPD_INDEX="36" NAME="IPLB_MIRQ" SIGNAME="mb_plb_PLB_MIRQ"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="I" MPD_INDEX="37" NAME="IPLB_MWrBTerm" SIGNAME="mb_plb_PLB_MWrBTerm"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="I" MPD_INDEX="38" NAME="IPLB_MWrDAck" SIGNAME="mb_plb_PLB_MWrDAck"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="I" MPD_INDEX="39" NAME="IPLB_MAddrAck" SIGNAME="mb_plb_PLB_MAddrAck"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="I" MPD_INDEX="40" NAME="IPLB_MRdBTerm" SIGNAME="mb_plb_PLB_MRdBTerm"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="I" MPD_INDEX="41" NAME="IPLB_MRdDAck" SIGNAME="mb_plb_PLB_MRdDAck"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="42" MSB="0" NAME="IPLB_MRdDBus" RIGHT="31" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="43" MSB="0" NAME="IPLB_MRdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_MRdWdAddr" VECFORMULA="[0:3]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRearbitrate" DIR="I" MPD_INDEX="44" NAME="IPLB_MRearbitrate" SIGNAME="mb_plb_PLB_MRearbitrate"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MSSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="IPLB_MSSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSSize" VECFORMULA="[0:1]"/><PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MTimeout" DIR="I" MPD_INDEX="46" NAME="IPLB_MTimeout" SIGNAME="mb_plb_PLB_MTimeout"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="DATA_READ" RIGHT="31" SIGNAME="dlmb_LMB_ReadDBus" VECFORMULA="[0:31]"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_Ready" DIR="I" MPD_INDEX="48" NAME="DREADY" SIGNAME="dlmb_LMB_Ready"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_Wait" DIR="I" MPD_INDEX="49" NAME="DWAIT" SIGNAME="dlmb_LMB_Wait"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_CE" DIR="I" MPD_INDEX="50" NAME="DCE" SIGNAME="dlmb_LMB_CE"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_UE" DIR="I" MPD_INDEX="51" NAME="DUE" SIGNAME="dlmb_LMB_UE"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="52" MSB="0" NAME="DATA_WRITE" RIGHT="31" SIGNAME="dlmb_M_DBus" VECFORMULA="[0:31]"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="53" MSB="0" NAME="DATA_ADDR" RIGHT="31" SIGNAME="dlmb_M_ABus" VECFORMULA="[0:31]"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_AddrStrobe" DIR="O" MPD_INDEX="54" NAME="D_AS" SIGNAME="dlmb_M_AddrStrobe"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_ReadStrobe" DIR="O" MPD_INDEX="55" NAME="READ_STROBE" SIGNAME="dlmb_M_ReadStrobe"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_WriteStrobe" DIR="O" MPD_INDEX="56" NAME="WRITE_STROBE" SIGNAME="dlmb_M_WriteStrobe"/><PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="BYTE_ENABLE" RIGHT="3" SIGNAME="dlmb_M_BE" VECFORMULA="[0:3]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_ABort" DIR="O" MPD_INDEX="58" NAME="DPLB_M_ABort" SIGNAME="mb_plb_M_ABort"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="59" MSB="0" NAME="DPLB_M_ABus" RIGHT="31" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:31]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="60" MSB="0" NAME="DPLB_M_UABus" RIGHT="31" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:31]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="61" MSB="0" NAME="DPLB_M_BE" RIGHT="3" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:(C_DPLB_DWIDTH-1)/8]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_busLock" DIR="O" MPD_INDEX="62" NAME="DPLB_M_busLock" SIGNAME="mb_plb_M_busLock"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_lockErr" DIR="O" MPD_INDEX="63" NAME="DPLB_M_lockErr" SIGNAME="mb_plb_M_lockErr"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="64" MSB="0" NAME="DPLB_M_MSize" RIGHT="1" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:1]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_priority" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="65" MSB="0" NAME="DPLB_M_priority" RIGHT="1" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:1]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_rdBurst" DIR="O" MPD_INDEX="66" NAME="DPLB_M_rdBurst" SIGNAME="mb_plb_M_rdBurst"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_request" DIR="O" MPD_INDEX="67" NAME="DPLB_M_request" SIGNAME="mb_plb_M_request"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_RNW" DIR="O" MPD_INDEX="68" NAME="DPLB_M_RNW" SIGNAME="mb_plb_M_RNW"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="69" MSB="0" NAME="DPLB_M_size" RIGHT="3" SIGNAME="mb_plb_M_size" VECFORMULA="[0:3]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="70" MSB="0" NAME="DPLB_M_TAttribute" RIGHT="15" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:15]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="71" MSB="0" NAME="DPLB_M_type" RIGHT="2" SIGNAME="mb_plb_M_type" VECFORMULA="[0:2]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_wrBurst" DIR="O" MPD_INDEX="72" NAME="DPLB_M_wrBurst" SIGNAME="mb_plb_M_wrBurst"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="73" MSB="0" NAME="DPLB_M_wrDBus" RIGHT="31" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="I" MPD_INDEX="74" NAME="DPLB_MBusy" SIGNAME="mb_plb_PLB_MBusy"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="I" MPD_INDEX="75" NAME="DPLB_MRdErr" SIGNAME="mb_plb_PLB_MRdErr"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="I" MPD_INDEX="76" NAME="DPLB_MWrErr" SIGNAME="mb_plb_PLB_MWrErr"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="I" MPD_INDEX="77" NAME="DPLB_MIRQ" SIGNAME="mb_plb_PLB_MIRQ"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="I" MPD_INDEX="78" NAME="DPLB_MWrBTerm" SIGNAME="mb_plb_PLB_MWrBTerm"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="I" MPD_INDEX="79" NAME="DPLB_MWrDAck" SIGNAME="mb_plb_PLB_MWrDAck"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="I" MPD_INDEX="80" NAME="DPLB_MAddrAck" SIGNAME="mb_plb_PLB_MAddrAck"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="I" MPD_INDEX="81" NAME="DPLB_MRdBTerm" SIGNAME="mb_plb_PLB_MRdBTerm"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="I" MPD_INDEX="82" NAME="DPLB_MRdDAck" SIGNAME="mb_plb_PLB_MRdDAck"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="83" MSB="0" NAME="DPLB_MRdDBus" RIGHT="31" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/><PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="84" MSB="0" NAME="DPLB_MRdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_MRdWdAddr" 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DIR="O" PHYSICAL="DPLB_M_ABus"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_UABus"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_BE"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_busLock"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_lockErr"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_MSize"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_priority"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_rdBurst"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_request"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_RNW"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_size"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_TAttribute"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_type"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_wrBurst"/><PORTMAP DIR="O" PHYSICAL="DPLB_M_wrDBus"/><PORTMAP DIR="I" PHYSICAL="DPLB_MBusy"/><PORTMAP DIR="I" PHYSICAL="DPLB_MRdErr"/><PORTMAP DIR="I" PHYSICAL="DPLB_MWrErr"/><PORTMAP DIR="I" PHYSICAL="DPLB_MIRQ"/><PORTMAP DIR="I" PHYSICAL="DPLB_MWrBTerm"/><PORTMAP DIR="I" PHYSICAL="DPLB_MWrDAck"/><PORTMAP DIR="I" PHYSICAL="DPLB_MAddrAck"/><PORTMAP DIR="I" PHYSICAL="DPLB_MRdBTerm"/><PORTMAP DIR="I" PHYSICAL="DPLB_MRdDAck"/><PORTMAP DIR="I" PHYSICAL="DPLB_MRdDBus"/><PORTMAP DIR="I" PHYSICAL="DPLB_MRdWdAddr"/><PORTMAP DIR="I" PHYSICAL="DPLB_MRearbitrate"/><PORTMAP DIR="I" PHYSICAL="DPLB_MSSize"/><PORTMAP DIR="I" PHYSICAL="DPLB_MTimeout"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="IPLB" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="CLK"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_ABort"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_ABus"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_UABus"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_BE"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_busLock"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_lockErr"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_MSize"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_priority"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_rdBurst"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_request"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_RNW"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_size"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_TAttribute"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_type"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_wrBurst"/><PORTMAP DIR="O" PHYSICAL="IPLB_M_wrDBus"/><PORTMAP DIR="I" PHYSICAL="IPLB_MBusy"/><PORTMAP DIR="I" PHYSICAL="IPLB_MRdErr"/><PORTMAP DIR="I" PHYSICAL="IPLB_MWrErr"/><PORTMAP DIR="I" PHYSICAL="IPLB_MIRQ"/><PORTMAP DIR="I" PHYSICAL="IPLB_MWrBTerm"/><PORTMAP DIR="I" PHYSICAL="IPLB_MWrDAck"/><PORTMAP DIR="I" PHYSICAL="IPLB_MAddrAck"/><PORTMAP DIR="I" PHYSICAL="IPLB_MRdBTerm"/><PORTMAP DIR="I" PHYSICAL="IPLB_MRdDAck"/><PORTMAP DIR="I" PHYSICAL="IPLB_MRdDBus"/><PORTMAP DIR="I" PHYSICAL="IPLB_MRdWdAddr"/><PORTMAP DIR="I" PHYSICAL="IPLB_MRearbitrate"/><PORTMAP DIR="I" PHYSICAL="IPLB_MSSize"/><PORTMAP DIR="I" PHYSICAL="IPLB_MTimeout"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="DLMB" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="CLK"/><PORTMAP DIR="I" PHYSICAL="RESET"/><PORTMAP DIR="I" PHYSICAL="DATA_READ"/><PORTMAP DIR="I" PHYSICAL="DREADY"/><PORTMAP DIR="I" PHYSICAL="DWAIT"/><PORTMAP DIR="I" PHYSICAL="DCE"/><PORTMAP DIR="I" PHYSICAL="DUE"/><PORTMAP DIR="O" PHYSICAL="DATA_WRITE"/><PORTMAP DIR="O" PHYSICAL="DATA_ADDR"/><PORTMAP DIR="O" PHYSICAL="D_AS"/><PORTMAP DIR="O" PHYSICAL="READ_STROBE"/><PORTMAP DIR="O" PHYSICAL="WRITE_STROBE"/><PORTMAP DIR="O" PHYSICAL="BYTE_ENABLE"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="ILMB" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="CLK"/><PORTMAP DIR="I" PHYSICAL="RESET"/><PORTMAP DIR="I" PHYSICAL="INSTR"/><PORTMAP DIR="I" PHYSICAL="IREADY"/><PORTMAP DIR="I" PHYSICAL="IWAIT"/><PORTMAP DIR="I" PHYSICAL="ICE"/><PORTMAP DIR="I" PHYSICAL="IUE"/><PORTMAP DIR="O" PHYSICAL="INSTR_ADDR"/><PORTMAP DIR="O" PHYSICAL="IFETCH"/><PORTMAP DIR="O" PHYSICAL="I_AS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="4" NAME="M_AXI_DP" PROTOCOL="AXI4LITE" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="CLK"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="CLK"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWADDR"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLEN"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWSIZE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWBURST"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLOCK"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWCACHE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWPROT"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWQOS"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWVALID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IP_AWREADY"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WDATA"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WSTRB"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WLAST"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WVALID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IP_WREADY"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BRESP"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BVALID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_BREADY"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARADDR"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLEN"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARSIZE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARBURST"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLOCK"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARCACHE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARPROT"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARQOS"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARVALID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IP_ARREADY"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RDATA"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RRESP"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RLAST"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RVALID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IP_RREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="104" NAME="M_AXI_DC" PROTOCOL="AXI4" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="CLK"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWADDR"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLEN"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWSIZE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWBURST"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLOCK"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWCACHE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWPROT"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWQOS"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWVALID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DC_AWREADY"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWUSER"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WDATA"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WSTRB"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WLAST"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WVALID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DC_WREADY"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WUSER"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BRESP"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BVALID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_BREADY"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BUSER"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARADDR"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLEN"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARSIZE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARBURST"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLOCK"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARCACHE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARPROT"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARQOS"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARVALID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DC_ARREADY"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARUSER"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RDATA"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RRESP"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RLAST"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RVALID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_DC_RREADY"/><PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RUSER"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="105" NAME="M_AXI_IC" PROTOCOL="AXI4" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="CLK"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWADDR"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLEN"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWSIZE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWBURST"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLOCK"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWCACHE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWPROT"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWQOS"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWVALID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IC_AWREADY"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWUSER"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WDATA"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WSTRB"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WLAST"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WVALID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IC_WREADY"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WUSER"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BRESP"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BVALID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_BREADY"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BUSER"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARADDR"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLEN"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARSIZE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARBURST"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLOCK"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARCACHE"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARPROT"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARQOS"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARVALID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IC_ARREADY"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARUSER"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RID"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RDATA"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RRESP"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RLAST"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RVALID"/><PORTMAP DIR="O" PHYSICAL="M_AXI_IC_RREADY"/><PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RUSER"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="microblaze_0_mdm_bus" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="106" NAME="DEBUG" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="DBG_CLK"/><PORTMAP DIR="I" PHYSICAL="DBG_TDI"/><PORTMAP DIR="O" PHYSICAL="DBG_TDO"/><PORTMAP DIR="I" PHYSICAL="DBG_REG_EN"/><PORTMAP DIR="I" PHYSICAL="DBG_SHIFT"/><PORTMAP DIR="I" PHYSICAL="DBG_CAPTURE"/><PORTMAP DIR="I" PHYSICAL="DBG_UPDATE"/><PORTMAP DIR="I" PHYSICAL="DEBUG_RST"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBTRACE2" MPD_INDEX="107" NAME="TRACE" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="Trace_Instruction"/><PORTMAP DIR="O" PHYSICAL="Trace_Valid_Instr"/><PORTMAP DIR="O" PHYSICAL="Trace_PC"/><PORTMAP DIR="O" PHYSICAL="Trace_Reg_Write"/><PORTMAP DIR="O" PHYSICAL="Trace_Reg_Addr"/><PORTMAP DIR="O" PHYSICAL="Trace_MSR_Reg"/><PORTMAP DIR="O" PHYSICAL="Trace_PID_Reg"/><PORTMAP DIR="O" PHYSICAL="Trace_New_Reg_Value"/><PORTMAP DIR="O" PHYSICAL="Trace_Exception_Taken"/><PORTMAP DIR="O" PHYSICAL="Trace_Exception_Kind"/><PORTMAP DIR="O" PHYSICAL="Trace_Jump_Taken"/><PORTMAP DIR="O" PHYSICAL="Trace_Delay_Slot"/><PORTMAP DIR="O" PHYSICAL="Trace_Data_Address"/><PORTMAP DIR="O" PHYSICAL="Trace_Data_Access"/><PORTMAP DIR="O" PHYSICAL="Trace_Data_Read"/><PORTMAP DIR="O" PHYSICAL="Trace_Data_Write"/><PORTMAP DIR="O" PHYSICAL="Trace_Data_Write_Value"/><PORTMAP DIR="O" PHYSICAL="Trace_Data_Byte_Enable"/><PORTMAP DIR="O" PHYSICAL="Trace_DCache_Req"/><PORTMAP DIR="O" PHYSICAL="Trace_DCache_Hit"/><PORTMAP DIR="O" PHYSICAL="Trace_DCache_Rdy"/><PORTMAP DIR="O" PHYSICAL="Trace_DCache_Read"/><PORTMAP DIR="O" PHYSICAL="Trace_ICache_Req"/><PORTMAP DIR="O" PHYSICAL="Trace_ICache_Hit"/><PORTMAP DIR="O" PHYSICAL="Trace_ICache_Rdy"/><PORTMAP DIR="O" PHYSICAL="Trace_OF_PipeRun"/><PORTMAP DIR="O" PHYSICAL="Trace_EX_PipeRun"/><PORTMAP DIR="O" PHYSICAL="Trace_MEM_PipeRun"/><PORTMAP DIR="O" PHYSICAL="Trace_MB_Halted"/><PORTMAP DIR="O" PHYSICAL="Trace_Jump_Hit"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="6" NAME="SFSL0" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="38" NAME="DRFSL0" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="7" NAME="MFSL0" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="39" NAME="DWFSL0" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="8" NAME="SFSL1" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="40" NAME="DRFSL1" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="9" NAME="MFSL1" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="41" NAME="DWFSL1" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="10" NAME="SFSL2" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="42" NAME="DRFSL2" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="11" NAME="MFSL2" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="43" NAME="DWFSL2" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="12" NAME="SFSL3" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="44" NAME="DRFSL3" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="13" NAME="MFSL3" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="45" NAME="DWFSL3" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="14" NAME="SFSL4" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="46" NAME="DRFSL4" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="15" NAME="MFSL4" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="47" NAME="DWFSL4" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="16" NAME="SFSL5" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="48" NAME="DRFSL5" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="17" NAME="MFSL5" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="49" NAME="DWFSL5" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="18" NAME="SFSL6" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="50" NAME="DRFSL6" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="19" NAME="MFSL6" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="51" NAME="DWFSL6" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="20" NAME="SFSL7" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="52" NAME="DRFSL7" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="21" NAME="MFSL7" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="53" NAME="DWFSL7" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="22" NAME="SFSL8" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="54" NAME="DRFSL8" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="23" NAME="MFSL8" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="55" NAME="DWFSL8" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="24" NAME="SFSL9" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="56" NAME="DRFSL9" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="25" NAME="MFSL9" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="57" NAME="DWFSL9" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="26" NAME="SFSL10" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="58" NAME="DRFSL10" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="27" NAME="MFSL10" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="59" NAME="DWFSL10" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="28" NAME="SFSL11" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="60" NAME="DRFSL11" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="29" NAME="MFSL11" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="61" NAME="DWFSL11" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="30" NAME="SFSL12" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="62" NAME="DRFSL12" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="31" NAME="MFSL12" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="63" NAME="DWFSL12" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="32" NAME="SFSL13" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="64" NAME="DRFSL13" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="33" NAME="MFSL13" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="65" NAME="DWFSL13" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="34" NAME="SFSL14" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="66" NAME="DRFSL14" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="35" NAME="MFSL14" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="67" NAME="DWFSL14" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="36" NAME="SFSL15" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="68" NAME="DRFSL15" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/><PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/><PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="37" NAME="MFSL15" TYPE="MASTER"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="69" NAME="DWFSL15" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/><PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/><PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/><PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/><PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="70" NAME="M0_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M0_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M0_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M0_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M0_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="71" NAME="S0_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S0_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S0_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S0_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S0_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="72" NAME="M1_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M1_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M1_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M1_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M1_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="73" NAME="S1_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S1_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S1_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S1_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S1_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="74" NAME="M2_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M2_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M2_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M2_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M2_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="75" NAME="S2_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S2_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S2_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S2_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S2_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="76" NAME="M3_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M3_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M3_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M3_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M3_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="77" NAME="S3_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S3_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S3_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S3_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S3_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="78" NAME="M4_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M4_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M4_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M4_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M4_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="79" NAME="S4_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S4_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S4_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S4_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S4_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="80" NAME="M5_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M5_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M5_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M5_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M5_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="81" NAME="S5_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S5_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S5_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S5_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S5_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="82" NAME="M6_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M6_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M6_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M6_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M6_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="83" NAME="S6_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S6_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S6_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S6_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S6_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="84" NAME="M7_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M7_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M7_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M7_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M7_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="85" NAME="S7_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S7_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S7_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S7_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S7_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="86" NAME="M8_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M8_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M8_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M8_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M8_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="87" NAME="S8_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S8_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S8_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S8_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S8_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="88" NAME="M9_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M9_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M9_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M9_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M9_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="89" NAME="S9_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S9_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S9_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S9_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S9_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="90" NAME="M10_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M10_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M10_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M10_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M10_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="91" NAME="S10_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S10_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S10_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S10_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S10_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="92" NAME="M11_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M11_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M11_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M11_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M11_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="93" NAME="S11_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S11_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S11_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S11_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S11_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="94" NAME="M12_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M12_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M12_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M12_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M12_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="95" NAME="S12_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S12_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S12_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S12_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S12_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="96" NAME="M13_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M13_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M13_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M13_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M13_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="97" NAME="S13_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S13_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S13_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S13_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S13_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="98" NAME="M14_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M14_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M14_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M14_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M14_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="99" NAME="S14_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S14_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S14_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S14_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S14_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="100" NAME="M15_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="M15_AXIS_TLAST"/><PORTMAP DIR="O" PHYSICAL="M15_AXIS_TDATA"/><PORTMAP DIR="O" PHYSICAL="M15_AXIS_TVALID"/><PORTMAP DIR="I" PHYSICAL="M15_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="101" NAME="S15_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S15_AXIS_TLAST"/><PORTMAP DIR="I" PHYSICAL="S15_AXIS_TDATA"/><PORTMAP DIR="I" PHYSICAL="S15_AXIS_TVALID"/><PORTMAP DIR="O" PHYSICAL="S15_AXIS_TREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTRUCTION="TRUE" MPD_INDEX="103" NAME="IXCL" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_CLK"/><PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_READ"/><PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_DATA"/><PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_CONTROL"/><PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_EXISTS"/><PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CLK"/><PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_WRITE"/><PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_DATA"/><PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CONTROL"/><PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_OUT_FULL"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_DATA="TRUE" MPD_INDEX="102" NAME="DXCL" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_CLK"/><PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_READ"/><PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_DATA"/><PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_CONTROL"/><PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_EXISTS"/><PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CLK"/><PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_WRITE"/><PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_DATA"/><PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CONTROL"/><PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_OUT_FULL"/></PORTMAPS></BUSINTERFACE></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="dlmb_cntlr" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K"><ACCESSROUTE><ROUTEPNT INDEX="0" INSTANCE="dlmb"/></ACCESSROUTE></MEMRANGE><MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="ilmb_cntlr" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K"><ACCESSROUTE><ROUTEPNT INDEX="0" INSTANCE="ilmb"/></ACCESSROUTE></MEMRANGE><MEMRANGE BASEDECIMAL="2214592512" BASENAME="C_BASEADDR" BASEVALUE="0x84000000" HIGHDECIMAL="2214658047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8400ffff" INSTANCE="RS232_DCE" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"><ACCESSROUTE><ROUTEPNT INDEX="0" INSTANCE="mb_plb"/></ACCESSROUTE></MEMRANGE><MEMRANGE BASEDECIMAL="2218786816" BASENAME="C_BASEADDR" BASEVALUE="0x84400000" HIGHDECIMAL="2218852351" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8440ffff" INSTANCE="mdm_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"><ACCESSROUTE><ROUTEPNT INDEX="0" INSTANCE="mb_plb"/></ACCESSROUTE></MEMRANGE><MEMRANGE BASEDECIMAL="2172649472" BASENAME="C_BASEADDR" BASEVALUE="0x81800000" HIGHDECIMAL="2172715007" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8180ffff" INSTANCE="xps_intc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"><ACCESSROUTE><ROUTEPNT INDEX="0" INSTANCE="mb_plb"/></ACCESSROUTE></MEMRANGE><MEMRANGE BASEDECIMAL="3439329280" BASENAME="C_BASEADDR" BASEVALUE="0xcd000000" HIGHDECIMAL="3439394815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xcd00ffff" INSTANCE="uart_plb_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"><ACCESSROUTE><ROUTEPNT INDEX="0" INSTANCE="mb_plb"/></ACCESSROUTE></MEMRANGE></MEMORYMAP><PERIPHERALS><PERIPHERAL INSTANCE="dlmb_cntlr"/><PERIPHERAL INSTANCE="ilmb_cntlr"/><PERIPHERAL INSTANCE="RS232_DCE"/><PERIPHERAL INSTANCE="mdm_0"/><PERIPHERAL INSTANCE="xps_intc_0"/><PERIPHERAL INSTANCE="uart_plb_0"/></PERIPHERALS><INTERRUPTINFO TYPE="TARGET"><SOURCE INSTANCE="xps_intc_0" INTC_INDEX="0"/></INTERRUPTINFO><RESOURCES><RESOURCE PERCENT="6" TOTAL="14752" TYPE="Slices" USED="926"/><RESOURCE PERCENT="3" TOTAL="29504" TYPE="Slice Flip Flops" USED="966"/><RESOURCE PERCENT="5" TOTAL="29504" TYPE="4 input LUTs" USED="1769"/><RESOURCE PERCENT="NA" TOTAL="NA" TYPE="IOs" USED="4034"/><RESOURCE PERCENT="0" TOTAL="250" TYPE="bonded IOBs" USED="0"/><RESOURCE PERCENT="8" TOTAL="36" TYPE="MULT18X18SIOs" USED="3"/></RESOURCES><TIMING FREQUNITS="MHz" MAXFREQ="87.719"><TIMECLK SIGNAME="DCACHE_FSL_OUT_CLK"/><TIMECLK SIGNAME="DBG_CLK"/><TIMECLK SIGNAME="DBG_UPDATE"/></TIMING></MODULE><MODULE BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" HWVERSION="1.05.a" INSTANCE="mb_plb" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="plb_v46"><DESCRIPTION TYPE="SHORT">Processor Local Bus (PLB) 4.6</DESCRIPTION><DESCRIPTION TYPE="LONG">'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_05_a/doc/plb_v46.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_PLBV46_NUM_MASTERS" TYPE="integer" VALUE="2"><DESCRIPTION>Number of PLB Masters</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_PLBV46_NUM_SLAVES" TYPE="integer" VALUE="4"><DESCRIPTION>Number of PLB Slaves</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PLBV46_MID_WIDTH" TYPE="integer" VALUE="1"><DESCRIPTION>PLB Master ID Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="3" NAME="C_PLBV46_AWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>PLB Address Bus Width</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_PLBV46_DWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>PLB Data Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="5" NAME="C_DCR_INTFCE" TYPE="integer" VALUE="0"><DESCRIPTION>Include DCR Interface and Error Registers</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="6" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0b1111111111"><DESCRIPTION>Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="7" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0b0000000000"><DESCRIPTION>High Address</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="8" NAME="C_DCR_AWIDTH" TYPE="integer" VALUE="10"><DESCRIPTION>DCR Address Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="9" NAME="C_DCR_DWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>DCR Data Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="10" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"><DESCRIPTION>External Reset Active High </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="11" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1"><DESCRIPTION>IRQ Active State </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="12" NAME="C_NUM_CLK_PLB2OPB_REARB" TYPE="integer" VALUE="5"><DESCRIPTION><qt>Number of PLB Clock Periods a PLB Master that Received a Rearbitrate from an OPB2PLB Bridge on a Read Operation is Denied Grant on the PLB Bus</qt></DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="13" NAME="C_ADDR_PIPELINING_TYPE" TYPE="integer" VALUE="1"><DESCRIPTION>Enable Address Pipelining Type</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_FAMILY" TYPE="string" VALUE="spartan3e"><DESCRIPTION>Device Family</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="15" NAME="C_P2P" TYPE="integer" VALUE="0"><DESCRIPTION>Optimize PLB for Point-to-point Topology</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="16" NAME="C_ARB_TYPE" TYPE="integer" VALUE="0"><DESCRIPTION>Selects the Arbitration Scheme</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/><PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGIS="RST" SIGNAME="sys_bus_reset"/><PORT DEF_SIGNAME="mb_plb_PLB_Rst" DIR="O" MPD_INDEX="2" NAME="PLB_Rst" SIGIS="RST" SIGNAME="mb_plb_PLB_Rst"/><PORT DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="SPLB_Rst" RIGHT="3" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_MPLB_Rst" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="4" MSB="0" NAME="MPLB_Rst" RIGHT="1" SIGIS="RST" SIGNAME="mb_plb_MPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="5" NAME="PLB_dcrAck" SIGNAME="__NOC__"/><PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="PLB_dcrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_DWIDTH-1]"/><PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="9" MPD_INDEX="7" MSB="0" NAME="DCR_ABus" RIGHT="9" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_AWIDTH-1]"/><PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="DCR_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_DWIDTH-1]"/><PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="DCR_Read" SIGNAME="__NOC__"/><PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="10" NAME="DCR_Write" SIGNAME="__NOC__"/><PORT DEF_SIGNAME="mb_plb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="11" MSB="0" NAME="M_ABus" RIGHT="63" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*32)-1]"/><PORT DEF_SIGNAME="mb_plb_M_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="12" MSB="0" NAME="M_UABus" RIGHT="63" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*32)-1]"/><PORT DEF_SIGNAME="mb_plb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="13" MSB="0" NAME="M_BE" RIGHT="7" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1]"/><PORT DEF_SIGNAME="mb_plb_M_RNW" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="14" MSB="0" NAME="M_RNW" RIGHT="1" SIGNAME="mb_plb_M_RNW" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_abort" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="15" MSB="0" NAME="M_abort" RIGHT="1" SIGNAME="mb_plb_M_abort" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_busLock" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="16" MSB="0" NAME="M_busLock" RIGHT="1" SIGNAME="mb_plb_M_busLock" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="M_TAttribute" RIGHT="31" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*16)-1]"/><PORT DEF_SIGNAME="mb_plb_M_lockErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="18" MSB="0" NAME="M_lockErr" RIGHT="1" SIGNAME="mb_plb_M_lockErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="19" MSB="0" NAME="M_MSize" RIGHT="3" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/><PORT DEF_SIGNAME="mb_plb_M_priority" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="20" MSB="0" NAME="M_priority" RIGHT="3" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/><PORT DEF_SIGNAME="mb_plb_M_rdBurst" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="21" MSB="0" NAME="M_rdBurst" RIGHT="1" SIGNAME="mb_plb_M_rdBurst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_request" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="M_request" RIGHT="1" SIGNAME="mb_plb_M_request" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="23" MSB="0" NAME="M_size" RIGHT="7" SIGNAME="mb_plb_M_size" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*4)-1]"/><PORT DEF_SIGNAME="mb_plb_M_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="5" MPD_INDEX="24" MSB="0" NAME="M_type" RIGHT="5" SIGNAME="mb_plb_M_type" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*3)-1]"/><PORT DEF_SIGNAME="mb_plb_M_wrBurst" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="25" MSB="0" NAME="M_wrBurst" RIGHT="1" SIGNAME="mb_plb_M_wrBurst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_M_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="26" MSB="0" NAME="M_wrDBus" RIGHT="63" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="27" MSB="0" NAME="Sl_addrAck" RIGHT="3" SIGNAME="mb_plb_Sl_addrAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="28" MSB="0" NAME="Sl_MRdErr" RIGHT="7" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="29" MSB="0" NAME="Sl_MWrErr" RIGHT="7" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="30" MSB="0" NAME="Sl_MBusy" RIGHT="7" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 ]"/><PORT DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="31" MSB="0" NAME="Sl_rdBTerm" RIGHT="3" SIGNAME="mb_plb_Sl_rdBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="32" MSB="0" NAME="Sl_rdComp" RIGHT="3" SIGNAME="mb_plb_Sl_rdComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="33" MSB="0" NAME="Sl_rdDAck" RIGHT="3" SIGNAME="mb_plb_Sl_rdDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="127" MPD_INDEX="34" MSB="0" NAME="Sl_rdDBus" RIGHT="127" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="35" MSB="0" NAME="Sl_rdWdAddr" RIGHT="15" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*4-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="36" MSB="0" NAME="Sl_rearbitrate" RIGHT="3" SIGNAME="mb_plb_Sl_rearbitrate" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_SSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="37" MSB="0" NAME="Sl_SSize" RIGHT="7" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*2-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_wait" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_wait" RIGHT="3" SIGNAME="mb_plb_Sl_wait" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_wrBTerm" RIGHT="3" SIGNAME="mb_plb_Sl_wrBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="Sl_wrComp" RIGHT="3" SIGNAME="mb_plb_Sl_wrComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_wrDAck" RIGHT="3" SIGNAME="mb_plb_Sl_wrDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="42" MSB="0" NAME="Sl_MIRQ" RIGHT="7" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="43" MSB="0" NAME="PLB_MIRQ" RIGHT="1" SIGNAME="mb_plb_PLB_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="44" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/><PORT DEF_SIGNAME="mb_plb_PLB_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="45" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/><PORT DEF_SIGNAME="mb_plb_PLB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="46" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:(C_PLBV46_DWIDTH/8)-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_MAddrAck" RIGHT="1" SIGNAME="mb_plb_PLB_MAddrAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MTimeout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="48" MSB="0" NAME="PLB_MTimeout" RIGHT="1" SIGNAME="mb_plb_PLB_MTimeout" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="49" MSB="0" NAME="PLB_MBusy" RIGHT="1" SIGNAME="mb_plb_PLB_MBusy" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="PLB_MRdErr" RIGHT="1" SIGNAME="mb_plb_PLB_MRdErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="51" MSB="0" NAME="PLB_MWrErr" RIGHT="1" SIGNAME="mb_plb_PLB_MWrErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="52" MSB="0" NAME="PLB_MRdBTerm" RIGHT="1" SIGNAME="mb_plb_PLB_MRdBTerm" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="PLB_MRdDAck" RIGHT="1" SIGNAME="mb_plb_PLB_MRdDAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="54" MSB="0" NAME="PLB_MRdDBus" RIGHT="63" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="55" MSB="0" NAME="PLB_MRdWdAddr" RIGHT="7" SIGNAME="mb_plb_PLB_MRdWdAddr" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*4)-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MRearbitrate" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="56" MSB="0" NAME="PLB_MRearbitrate" RIGHT="1" SIGNAME="mb_plb_PLB_MRearbitrate" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="57" MSB="0" NAME="PLB_MWrBTerm" RIGHT="1" SIGNAME="mb_plb_PLB_MWrBTerm" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="58" MSB="0" NAME="PLB_MWrDAck" RIGHT="1" SIGNAME="mb_plb_PLB_MWrDAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MSSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="59" MSB="0" NAME="PLB_MSSize" RIGHT="3" SIGNAME="mb_plb_PLB_MSSize" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="O" MPD_INDEX="60" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/><PORT DEF_SIGNAME="mb_plb_PLB_RNW" DIR="O" MPD_INDEX="61" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/><PORT DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="O" MPD_INDEX="62" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/><PORT DEF_SIGNAME="mb_plb_PLB_abort" DIR="O" MPD_INDEX="63" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/><PORT DEF_SIGNAME="mb_plb_PLB_busLock" DIR="O" MPD_INDEX="64" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/><PORT DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="65" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/><PORT DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="O" MPD_INDEX="66" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/><PORT DEF_SIGNAME="mb_plb_PLB_masterID" DIR="O" MPD_INDEX="67" NAME="PLB_masterID" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:C_PLBV46_MID_WIDTH-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="68" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/><PORT DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="69" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/><PORT DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="70" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/><PORT DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="O" MPD_INDEX="71" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/><PORT DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="O" MPD_INDEX="72" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/><PORT DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="O" MPD_INDEX="73" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/><PORT DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="74" MSB="0" NAME="PLB_rdPrim" RIGHT="3" SIGNAME="mb_plb_PLB_rdPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="75" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/><PORT DEF_SIGNAME="mb_plb_PLB_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="76" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/><PORT DEF_SIGNAME="mb_plb_PLB_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="77" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/><PORT DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="O" MPD_INDEX="78" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/><PORT DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="79" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:C_PLBV46_DWIDTH-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="80" MSB="0" NAME="PLB_wrPrim" RIGHT="3" SIGNAME="mb_plb_PLB_wrPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_SaddrAck" DIR="O" MPD_INDEX="81" NAME="PLB_SaddrAck" SIGNAME="mb_plb_PLB_SaddrAck"/><PORT DEF_SIGNAME="mb_plb_PLB_SMRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="82" MSB="0" NAME="PLB_SMRdErr" RIGHT="1" SIGNAME="mb_plb_PLB_SMRdErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_SMWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="83" MSB="0" NAME="PLB_SMWrErr" RIGHT="1" SIGNAME="mb_plb_PLB_SMWrErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_SMBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="84" MSB="0" NAME="PLB_SMBusy" RIGHT="1" SIGNAME="mb_plb_PLB_SMBusy" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_SrdBTerm" DIR="O" MPD_INDEX="85" NAME="PLB_SrdBTerm" SIGNAME="mb_plb_PLB_SrdBTerm"/><PORT DEF_SIGNAME="mb_plb_PLB_SrdComp" DIR="O" MPD_INDEX="86" NAME="PLB_SrdComp" SIGNAME="mb_plb_PLB_SrdComp"/><PORT DEF_SIGNAME="mb_plb_PLB_SrdDAck" DIR="O" MPD_INDEX="87" NAME="PLB_SrdDAck" SIGNAME="mb_plb_PLB_SrdDAck"/><PORT DEF_SIGNAME="mb_plb_PLB_SrdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="88" MSB="0" NAME="PLB_SrdDBus" RIGHT="31" SIGNAME="mb_plb_PLB_SrdDBus" VECFORMULA="[0:C_PLBV46_DWIDTH-1]"/><PORT DEF_SIGNAME="mb_plb_PLB_SrdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="89" MSB="0" NAME="PLB_SrdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_SrdWdAddr" VECFORMULA="[0:3]"/><PORT DEF_SIGNAME="mb_plb_PLB_Srearbitrate" DIR="O" MPD_INDEX="90" NAME="PLB_Srearbitrate" SIGNAME="mb_plb_PLB_Srearbitrate"/><PORT DEF_SIGNAME="mb_plb_PLB_Sssize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="91" MSB="0" NAME="PLB_Sssize" RIGHT="1" SIGNAME="mb_plb_PLB_Sssize" VECFORMULA="[0:1]"/><PORT DEF_SIGNAME="mb_plb_PLB_Swait" DIR="O" MPD_INDEX="92" NAME="PLB_Swait" SIGNAME="mb_plb_PLB_Swait"/><PORT DEF_SIGNAME="mb_plb_PLB_SwrBTerm" DIR="O" MPD_INDEX="93" NAME="PLB_SwrBTerm" SIGNAME="mb_plb_PLB_SwrBTerm"/><PORT DEF_SIGNAME="mb_plb_PLB_SwrComp" DIR="O" MPD_INDEX="94" NAME="PLB_SwrComp" SIGNAME="mb_plb_PLB_SwrComp"/><PORT DEF_SIGNAME="mb_plb_PLB_SwrDAck" DIR="O" MPD_INDEX="95" NAME="PLB_SwrDAck" SIGNAME="mb_plb_PLB_SwrDAck"/><PORT DIR="O" MPD_INDEX="96" NAME="Bus_Error_Det" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="DCR" BUSSTD_PSF="DCR" IS_VALID="FALSE" MPD_INDEX="0" NAME="SDCR" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="PLB_dcrAck"/><PORTMAP DIR="O" PHYSICAL="PLB_dcrDBus"/><PORTMAP DIR="I" PHYSICAL="DCR_ABus"/><PORTMAP DIR="I" PHYSICAL="DCR_DBus"/><PORTMAP DIR="I" PHYSICAL="DCR_Read"/><PORTMAP DIR="I" PHYSICAL="DCR_Write"/></PORTMAPS></BUSINTERFACE></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="1023" BASENAME="C_BASEADDR" BASEVALUE="0b1111111111" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0b0000000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x08" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="SDCR"/></SLAVES></MEMRANGE></MEMORYMAP><RESOURCES><RESOURCE PERCENT="1" TOTAL="14752" TYPE="Slices" USED="224"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="Slice Flip Flops" USED="154"/><RESOURCE PERCENT="1" TOTAL="29504" TYPE="4 input LUTs" USED="381"/><RESOURCE PERCENT="NA" TOTAL="NA" TYPE="IOs" USED="876"/><RESOURCE PERCENT="0" TOTAL="250" TYPE="bonded IOBs" USED="0"/></RESOURCES><TIMING FREQUNITS="MHz" MAXFREQ="155.933"><TIMECLK SIGNAME="PLB_Clk"/></TIMING></MODULE><MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="ilmb" IPTYPE="BUS" MHS_INDEX="2" MODCLASS="BUS" MODTYPE="lmb_v10"><DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION><DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"><DESCRIPTION>Number of Bus Slaves </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Address Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Data Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"><DESCRIPTION>Active High External Reset</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/><PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGNAME="sys_bus_reset"/><PORT DEF_SIGNAME="ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="ilmb_LMB_Rst"/><PORT DEF_SIGNAME="ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT DEF_SIGNAME="ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="ilmb_M_ReadStrobe"/><PORT DEF_SIGNAME="ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="ilmb_M_WriteStrobe"/><PORT DEF_SIGNAME="ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="ilmb_M_AddrStrobe"/><PORT DEF_SIGNAME="ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT DEF_SIGNAME="ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/><PORT DEF_SIGNAME="ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/><PORT DEF_SIGNAME="ilmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="ilmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="ilmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="ilmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="ilmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="ilmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="ilmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT DEF_SIGNAME="ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="ilmb_LMB_ReadStrobe"/><PORT DEF_SIGNAME="ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="ilmb_LMB_WriteStrobe"/><PORT DEF_SIGNAME="ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="ilmb_LMB_AddrStrobe"/><PORT DEF_SIGNAME="ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT DEF_SIGNAME="ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT DEF_SIGNAME="ilmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="ilmb_LMB_Ready"/><PORT DEF_SIGNAME="ilmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="ilmb_LMB_Wait"/><PORT DEF_SIGNAME="ilmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="ilmb_LMB_UE"/><PORT DEF_SIGNAME="ilmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="ilmb_LMB_CE"/><PORT DEF_SIGNAME="ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/></PORTS><BUSINTERFACES/><IOINTERFACES><IOINTERFACE MPD_INDEX="0" NAME="reset_0"/></IOINTERFACES><RESOURCES><RESOURCE PERCENT="0" TOTAL="14752" TYPE="Slices" USED="1"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="Slice Flip Flops" USED="1"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="4 input LUTs" USED="1"/><RESOURCE PERCENT="NA" TOTAL="NA" TYPE="IOs" USED="217"/><RESOURCE PERCENT="0" TOTAL="250" TYPE="bonded IOBs" USED="0"/></RESOURCES><TIMING FREQUNITS="MHz" MAXFREQ="249.128"><TIMECLK SIGNAME="LMB_Clk"/></TIMING></MODULE><MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="dlmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10"><DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION><DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"><DESCRIPTION>Number of Bus Slaves </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Address Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Data Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"><DESCRIPTION>Active High External Reset</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/><PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGNAME="sys_bus_reset"/><PORT DEF_SIGNAME="dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="dlmb_LMB_Rst"/><PORT DEF_SIGNAME="dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT DEF_SIGNAME="dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="dlmb_M_ReadStrobe"/><PORT DEF_SIGNAME="dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="dlmb_M_WriteStrobe"/><PORT DEF_SIGNAME="dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="dlmb_M_AddrStrobe"/><PORT DEF_SIGNAME="dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT DEF_SIGNAME="dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/><PORT DEF_SIGNAME="dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/><PORT DEF_SIGNAME="dlmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="dlmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="dlmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="dlmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="dlmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="dlmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="dlmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/><PORT DEF_SIGNAME="dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT DEF_SIGNAME="dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="dlmb_LMB_ReadStrobe"/><PORT DEF_SIGNAME="dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="dlmb_LMB_WriteStrobe"/><PORT DEF_SIGNAME="dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="dlmb_LMB_AddrStrobe"/><PORT DEF_SIGNAME="dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT DEF_SIGNAME="dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT DEF_SIGNAME="dlmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="dlmb_LMB_Ready"/><PORT DEF_SIGNAME="dlmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="dlmb_LMB_Wait"/><PORT DEF_SIGNAME="dlmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="dlmb_LMB_UE"/><PORT DEF_SIGNAME="dlmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="dlmb_LMB_CE"/><PORT DEF_SIGNAME="dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/></PORTS><BUSINTERFACES/><IOINTERFACES><IOINTERFACE MPD_INDEX="0" NAME="reset_0"/></IOINTERFACES><RESOURCES><RESOURCE PERCENT="0" TOTAL="14752" TYPE="Slices" USED="1"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="Slice Flip Flops" USED="1"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="4 input LUTs" USED="1"/><RESOURCE PERCENT="NA" TOTAL="NA" TYPE="IOs" USED="217"/><RESOURCE PERCENT="0" TOTAL="250" TYPE="bonded IOBs" USED="0"/></RESOURCES><TIMING FREQUNITS="MHz" MAXFREQ="249.128"><TIMECLK SIGNAME="LMB_Clk"/></TIMING></MODULE><MODULE HWVERSION="3.00.a" INSTANCE="dlmb_cntlr" IPTYPE="PERIPHERAL" MHS_INDEX="4" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr"><DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION><DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>LMB BRAM Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"><DESCRIPTION>LMB BRAM High Address</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan3e"/><PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x80000000"><DESCRIPTION>LMB Address Decode Mask</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Address Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Data Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0"><DESCRIPTION>Error Correction Code </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0"><DESCRIPTION>Select Interconnect </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0"><DESCRIPTION>Fault Inject Registers </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0"><DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0"><DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0"><DESCRIPTION>ECC Status and Control Register </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0"><DESCRIPTION>ECC On/Off Register </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1"><DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0"><DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2"><DESCRIPTION>Write Access setting </DESCRIPTION></PARAMETER><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"><DESCRIPTION>Base Address for PLB Interface</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>High Address for PLB Interface</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>PLB Address Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>PLB Data Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Number of PLB Masters</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"><DESCRIPTION>Frequency of PLB Slave</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"><DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"><DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"><DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT BUS="SLMB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="dlmb_LMB_Rst"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="dlmb_LMB_AddrStrobe"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="dlmb_LMB_ReadStrobe"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="dlmb_LMB_WriteStrobe"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="dlmb_Sl_Ready"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="dlmb_Sl_Wait"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="dlmb_Sl_UE"/><PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="dlmb_Sl_CE"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="dlmb_port_BRAM_Rst"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="dlmb_port_BRAM_Clk"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="dlmb_port_BRAM_EN"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="dlmb_port_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/><PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="LMB_Clk"/><PORTMAP DIR="I" PHYSICAL="LMB_Rst"/><PORTMAP DIR="I" PHYSICAL="LMB_ABus"/><PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/><PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/><PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/><PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/><PORTMAP DIR="I" PHYSICAL="LMB_BE"/><PORTMAP DIR="O" PHYSICAL="Sl_DBus"/><PORTMAP DIR="O" PHYSICAL="Sl_Ready"/><PORTMAP DIR="O" PHYSICAL="Sl_Wait"/><PORTMAP DIR="O" PHYSICAL="Sl_UE"/><PORTMAP DIR="O" PHYSICAL="Sl_CE"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="dlmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/><PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/><PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/><PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/><PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/><PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/><PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/></PORTMAPS></BUSINTERFACE></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K"><SLAVES><SLAVE BUSINTERFACE="SLMB"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="SPLB_CTRL"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="S_AXI_CTRL"/></SLAVES></MEMRANGE></MEMORYMAP><RESOURCES><RESOURCE PERCENT="0" TOTAL="14752" TYPE="Slices" USED="3"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="Slice Flip Flops" USED="2"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="4 input LUTs" USED="6"/><RESOURCE PERCENT="NA" TOTAL="NA" TYPE="IOs" USED="556"/><RESOURCE PERCENT="0" TOTAL="250" TYPE="bonded IOBs" USED="0"/></RESOURCES></MODULE><MODULE HWVERSION="3.00.a" INSTANCE="ilmb_cntlr" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr"><DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION><DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>LMB BRAM Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"><DESCRIPTION>LMB BRAM High Address</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan3e"/><PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x80000000"><DESCRIPTION>LMB Address Decode Mask</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Address Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>LMB Data Bus Width </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0"><DESCRIPTION>Error Correction Code </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0"><DESCRIPTION>Select Interconnect </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0"><DESCRIPTION>Fault Inject Registers </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0"><DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0"><DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0"><DESCRIPTION>ECC Status and Control Register </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0"><DESCRIPTION>ECC On/Off Register </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1"><DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0"><DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2"><DESCRIPTION>Write Access setting </DESCRIPTION></PARAMETER><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"><DESCRIPTION>Base Address for PLB Interface</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>High Address for PLB Interface</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>PLB Address Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>PLB Data Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Number of PLB Masters</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"><DESCRIPTION>Frequency of PLB Slave</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"><DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"><DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"><DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"><DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT BUS="SLMB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="ilmb_LMB_Rst"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="ilmb_LMB_AddrStrobe"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="ilmb_LMB_ReadStrobe"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="ilmb_LMB_WriteStrobe"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="ilmb_Sl_Ready"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="ilmb_Sl_Wait"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="ilmb_Sl_UE"/><PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="ilmb_Sl_CE"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="ilmb_port_BRAM_Rst"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="ilmb_port_BRAM_Clk"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="ilmb_port_BRAM_EN"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="ilmb_port_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/><PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/><PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/><PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="LMB_Clk"/><PORTMAP DIR="I" PHYSICAL="LMB_Rst"/><PORTMAP DIR="I" PHYSICAL="LMB_ABus"/><PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/><PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/><PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/><PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/><PORTMAP DIR="I" PHYSICAL="LMB_BE"/><PORTMAP DIR="O" PHYSICAL="Sl_DBus"/><PORTMAP DIR="O" PHYSICAL="Sl_Ready"/><PORTMAP DIR="O" PHYSICAL="Sl_Wait"/><PORTMAP DIR="O" PHYSICAL="Sl_UE"/><PORTMAP DIR="O" PHYSICAL="Sl_CE"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="ilmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/><PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/><PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/><PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/><PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/><PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/><PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/><PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/><PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/><PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/><PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/></PORTMAPS></BUSINTERFACE></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K"><SLAVES><SLAVE BUSINTERFACE="SLMB"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="SPLB_CTRL"/></SLAVES></MEMRANGE><MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U"><SLAVES><SLAVE BUSINTERFACE="S_AXI_CTRL"/></SLAVES></MEMRANGE></MEMORYMAP><RESOURCES><RESOURCE PERCENT="0" TOTAL="14752" TYPE="Slices" USED="3"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="Slice Flip Flops" USED="2"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="4 input LUTs" USED="6"/><RESOURCE PERCENT="NA" TOTAL="NA" TYPE="IOs" USED="556"/><RESOURCE PERCENT="0" TOTAL="250" TYPE="bonded IOBs" USED="0"/></RESOURCES></MODULE><MODULE HWVERSION="1.00.a" INSTANCE="lmb_bram" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY" MODTYPE="bram_block"><DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION><DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000"><DESCRIPTION>Size of BRAM(s) in Bytes</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>Data Width of Port A and B</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32"><DESCRIPTION>Address Width of Port A and B</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4"><DESCRIPTION>Number of Byte Write Enables</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan3e"><DESCRIPTION>Device Family</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="ilmb_port_BRAM_Rst"/><PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="ilmb_port_BRAM_Clk"/><PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="ilmb_port_BRAM_EN"/><PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="ilmb_port_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/><PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/><PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/><PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/><PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="dlmb_port_BRAM_Rst"/><PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="dlmb_port_BRAM_Clk"/><PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="dlmb_port_BRAM_EN"/><PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="dlmb_port_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/><PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/><PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/><PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="ilmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/><PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/><PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/><PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/><PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/><PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/><PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="dlmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/><PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/><PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/><PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/><PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/><PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/><PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/></PORTMAPS></BUSINTERFACE></BUSINTERFACES><RESOURCES><RESOURCE PERCENT="0" TOTAL="14752" TYPE="Slices" USED="0"/><RESOURCE PERCENT="NA" TOTAL="NA" TYPE="IOs" USED="206"/><RESOURCE PERCENT="0" TOTAL="250" TYPE="bonded IOBs" USED="0"/><RESOURCE PERCENT="11" TOTAL="36" TYPE="BRAMs" USED="4"/></RESOURCES></MODULE><MODULE HWVERSION="1.01.a" INSTANCE="RS232_DCE" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="PERIPHERAL" MODTYPE="xps_uartlite"><DESCRIPTION TYPE="SHORT">XPS UART (Lite)</DESCRIPTION><DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_uartlite_v1_01_a/doc/xps_uartlite.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e"><DESCRIPTION>Device Family</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_SPLB_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"><DESCRIPTION>Clock Frequency of PLB Slave</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="6" MPD_INDEX="2" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x84000000"><DESCRIPTION>Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="7" MPD_INDEX="3" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8400ffff"><DESCRIPTION>High Address</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="4" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>PLB Address Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="5" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>PLB Data Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="6" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="7" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2"><DESCRIPTION>Number of PLB Masters</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="9" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="11" NAME="C_BAUDRATE" TYPE="INTEGER" VALUE="115200"><DESCRIPTION>UART Lite Baud Rate </DESCRIPTION><DESCRIPTION>Baud Rate</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="12" NAME="C_DATA_BITS" TYPE="INTEGER" VALUE="8"><DESCRIPTION>Number of Data Bits in a Serial Frame</DESCRIPTION><DESCRIPTION>Data Bits</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_USE_PARITY" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Use Parity </DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="14" NAME="C_ODD_PARITY" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Parity Type </DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT DIR="I" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="42" NAME="RX" SIGNAME="fpga_0_RS232_DCE_RX_pin"><DESCRIPTION>Serial Data In</DESCRIPTION></PORT><PORT DIR="O" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="43" NAME="TX" SIGNAME="fpga_0_RS232_DCE_TX_pin"><DESCRIPTION>Serial Data Out</DESCRIPTION></PORT><PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="44" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_DCE_Interrupt"/><PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="3" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" MPD_INDEX="4" NAME="PLB_masterID" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="5" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="6" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="8" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="10" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="11" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="12" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="13" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="14" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="15" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="16" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="17" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="33" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="34" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="35" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="37" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="38" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="40" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/><PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/><PORTMAP DIR="I" PHYSICAL="PLB_ABus"/><PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/><PORTMAP DIR="I" PHYSICAL="PLB_masterID"/><PORTMAP DIR="I" PHYSICAL="PLB_RNW"/><PORTMAP DIR="I" PHYSICAL="PLB_BE"/><PORTMAP DIR="I" PHYSICAL="PLB_size"/><PORTMAP DIR="I" PHYSICAL="PLB_type"/><PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/><PORTMAP DIR="I" PHYSICAL="PLB_UABus"/><PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/><PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/><PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/><PORTMAP DIR="I" PHYSICAL="PLB_abort"/><PORTMAP DIR="I" PHYSICAL="PLB_busLock"/><PORTMAP DIR="I" PHYSICAL="PLB_MSize"/><PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/><PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/><PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/><PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/><PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/><PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/><PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/><PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/><PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/><PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/><PORTMAP DIR="O" PHYSICAL="Sl_SSize"/><PORTMAP DIR="O" PHYSICAL="Sl_wait"/><PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/><PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/><PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/><PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/><PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/><PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/><PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/><PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/><PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/><PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/><PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/><PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/><PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/></PORTMAPS></BUSINTERFACE></BUSINTERFACES><IOINTERFACES><IOINTERFACE MPD_INDEX="0" NAME="uart_0" TYPE="XIL_UART_V1"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="RX"/><PORTMAP DIR="O" PHYSICAL="TX"/></PORTMAPS></IOINTERFACE></IOINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="2214592512" BASENAME="C_BASEADDR" BASEVALUE="0x84000000" HIGHDECIMAL="2214658047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8400ffff" MEMTYPE="REGISTER" MINSIZE="0x10" SIZE="65536" SIZEABRV="64K"><SLAVES><SLAVE BUSINTERFACE="SPLB"/></SLAVES></MEMRANGE></MEMORYMAP><INTERRUPTINFO TYPE="SOURCE"><TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="0"/></INTERRUPTINFO><RESOURCES><RESOURCE PERCENT="0" TOTAL="14752" TYPE="Slices" USED="106"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="Slice Flip Flops" USED="142"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="4 input LUTs" USED="131"/><RESOURCE PERCENT="NA" TOTAL="NA" TYPE="IOs" USED="204"/><RESOURCE PERCENT="0" TOTAL="250" TYPE="bonded IOBs" USED="0"/></RESOURCES><TIMING FREQUNITS="MHz" MAXFREQ="150.015"><TIMECLK SIGNAME="SPLB_Clk"/></TIMING></MODULE><MODULE HWVERSION="4.01.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="IP" MODTYPE="clock_generator"><DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION><DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_01_a/doc/clock_generator.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e"><DESCRIPTION>Family</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="3s1600e"><DESCRIPTION>Device</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="fg320"><DESCRIPTION>Package</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-4"><DESCRIPTION>Speed Grade</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="50000000"><DESCRIPTION>Input Clock Frequency (Hz) </DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="50000000"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase </DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Varaible Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION> Varaible Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION> Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION> Variable Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Clock Deskew</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Frequency (Hz)</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="INTEGER" VALUE="0"><DESCRIPTION>Required Phase</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Required Group</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE"><DESCRIPTION>Buffered</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE"><DESCRIPTION>Variable Phase Shift</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" VALUE="1"/><PARAMETER MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE"><DESCRIPTION>Clock Primitive Feedback Buffer</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="94" NAME="C_CLK_GEN" VALUE="UPDATE"/></PARAMETERS><PORTS><PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="CLK_S"/><PORT CLKFREQUENCY="50000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/><PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="sys_rst_s"/><PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="24" NAME="LOCKED" SIGNAME="Dcm_all_locked"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="I" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/><PORT DIR="I" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/><PORT DIR="I" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/><PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/></PORTS><BUSINTERFACES/><RESOURCES><RESOURCE PERCENT="0" TOTAL="14752" TYPE="Slices" USED="2"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="Slice Flip Flops" USED="4"/><RESOURCE PERCENT="NA" TOTAL="NA" TYPE="IOs" USED="25"/><RESOURCE PERCENT="0" TOTAL="250" TYPE="bonded IOBs" USED="0"/><RESOURCE PERCENT="4" TOTAL="24" TYPE="GCLKs" USED="1"/><RESOURCE PERCENT="12" TOTAL="8" TYPE="DCMs" USED="1"/></RESOURCES><TIMING FREQUNITS="MHz" MAXFREQ="758.150"><TIMECLK SIGNAME="CLKIN"/></TIMING></MODULE><MODULE HWVERSION="2.00.b" INSTANCE="mdm_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="DEBUG" MODTYPE="mdm"><DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION><DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e"><DESCRIPTION>Device Family</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2"><DESCRIPTION>Specifies the JTAG user-defined register used </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Specifies the Bus Interface for the JTAG UART </DESCRIPTION></PARAMETER><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x84400000"><DESCRIPTION>Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x8440ffff"><DESCRIPTION>High Address</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>PLB Address Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>PLB Data Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2"><DESCRIPTION>Number of PLB Masters</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="12" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Number of MicroBlaze debug ports </DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="13" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Enable JTAG UART </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="14" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>AXI Address Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="15" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>AXI Data Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"><DESCRIPTION>AXI4LITE protocal</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="Debug_SYS_Rst" SIGNAME="Debug_SYS_Rst"/><PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/><PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK"/><PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="8" NAME="S_AXI_AWREADY" SIGNAME="__NOC__"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_DATA_WIDTH/8-1):0]"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="11" NAME="S_AXI_WVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="S_AXI_WREADY" SIGNAME="__NOC__"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="S_AXI_BVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="15" NAME="S_AXI_BREADY" SIGNAME="__NOC__"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="17" NAME="S_AXI_ARVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="18" NAME="S_AXI_ARREADY" SIGNAME="__NOC__"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="21" NAME="S_AXI_RVALID" SIGNAME="__NOC__"/><PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="S_AXI_RREADY" SIGNAME="__NOC__"/><PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="23" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="24" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="25" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="26" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="27" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="28" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="29" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="30" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" MPD_INDEX="31" NAME="PLB_masterID" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="32" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="33" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="34" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="35" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="37" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="38" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="39" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="40" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="41" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="42" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="43" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="44" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="48" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="49" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="51" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="52" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="53" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="54" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="55" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="58" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="59" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="60" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="61" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="62" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="63" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="64" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Clk" DIR="O" MPD_INDEX="65" NAME="Dbg_Clk_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Clk"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_TDI" DIR="O" MPD_INDEX="66" NAME="Dbg_TDI_0" SIGNAME="microblaze_0_mdm_bus_Dbg_TDI"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_TDO" DIR="I" MPD_INDEX="67" NAME="Dbg_TDO_0" SIGNAME="microblaze_0_mdm_bus_Dbg_TDO"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Reg_En" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="68" MSB="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGNAME="microblaze_0_mdm_bus_Dbg_Reg_En" VECFORMULA="[0:7]"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Capture" DIR="O" MPD_INDEX="69" NAME="Dbg_Capture_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Capture"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Shift" DIR="O" MPD_INDEX="70" NAME="Dbg_Shift_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Shift"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Update" DIR="O" MPD_INDEX="71" NAME="Dbg_Update_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Update"/><PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Debug_Rst" DIR="O" MPD_INDEX="72" NAME="Dbg_Rst_0" SIGNAME="microblaze_0_mdm_bus_Debug_Rst"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="Dbg_Clk_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="Dbg_TDI_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="Dbg_TDO_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="76" MSB="0" NAME="Dbg_Reg_En_1" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="77" NAME="Dbg_Capture_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="Dbg_Shift_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="79" NAME="Dbg_Update_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="80" NAME="Dbg_Rst_1" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="Dbg_Clk_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="82" NAME="Dbg_TDI_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="Dbg_TDO_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="84" MSB="0" NAME="Dbg_Reg_En_2" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="85" NAME="Dbg_Capture_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="86" NAME="Dbg_Shift_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="Dbg_Update_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="Dbg_Rst_2" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="89" NAME="Dbg_Clk_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="Dbg_TDI_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="Dbg_TDO_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="92" MSB="0" NAME="Dbg_Reg_En_3" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="Dbg_Capture_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="Dbg_Shift_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="Dbg_Update_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="Dbg_Rst_3" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="Dbg_Clk_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="98" NAME="Dbg_TDI_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="Dbg_TDO_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="100" MSB="0" NAME="Dbg_Reg_En_4" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="Dbg_Capture_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="Dbg_Shift_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="Dbg_Update_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="Dbg_Rst_4" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="Dbg_Clk_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="Dbg_TDI_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="107" NAME="Dbg_TDO_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="108" MSB="0" NAME="Dbg_Reg_En_5" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="Dbg_Capture_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="Dbg_Shift_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="Dbg_Update_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="112" NAME="Dbg_Rst_5" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="Dbg_Clk_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="114" NAME="Dbg_TDI_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="115" NAME="Dbg_TDO_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="116" MSB="0" NAME="Dbg_Reg_En_6" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="Dbg_Capture_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="118" NAME="Dbg_Shift_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="119" NAME="Dbg_Update_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="Dbg_Rst_6" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="Dbg_Clk_7" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="Dbg_TDI_7" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="Dbg_TDO_7" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="124" MSB="0" NAME="Dbg_Reg_En_7" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="125" NAME="Dbg_Capture_7" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="126" NAME="Dbg_Shift_7" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="Dbg_Update_7" SIGNAME="__NOC__"/><PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="128" NAME="Dbg_Rst_7" SIGNAME="__NOC__"/><PORT DEF_SIGNAME="bscan_tdi" DIR="O" MPD_INDEX="129" NAME="bscan_tdi" SIGNAME="bscan_tdi"/><PORT DEF_SIGNAME="bscan_reset" DIR="O" MPD_INDEX="130" NAME="bscan_reset" SIGNAME="bscan_reset"/><PORT DEF_SIGNAME="bscan_shift" DIR="O" MPD_INDEX="131" NAME="bscan_shift" SIGNAME="bscan_shift"/><PORT DEF_SIGNAME="bscan_update" DIR="O" MPD_INDEX="132" NAME="bscan_update" SIGNAME="bscan_update"/><PORT DEF_SIGNAME="bscan_capture" DIR="O" MPD_INDEX="133" NAME="bscan_capture" SIGNAME="bscan_capture"/><PORT DEF_SIGNAME="bscan_sel1" DIR="O" MPD_INDEX="134" NAME="bscan_sel1" SIGNAME="bscan_sel1"/><PORT DEF_SIGNAME="bscan_drck1" DIR="O" MPD_INDEX="135" NAME="bscan_drck1" SIGNAME="bscan_drck1"/><PORT DEF_SIGNAME="bscan_tdo1" DIR="I" MPD_INDEX="136" NAME="bscan_tdo1" SIGNAME="bscan_tdo1"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="Ext_JTAG_DRCK" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="138" NAME="Ext_JTAG_RESET" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="140" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="143" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/><PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="144" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/><PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/><PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/><PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/><PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/><PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/><PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/><PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/><PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/><PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/><PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/><PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/><PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/><PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/><PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/><PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/><PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/><PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/><PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SPLB" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/><PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/><PORTMAP DIR="I" PHYSICAL="PLB_ABus"/><PORTMAP DIR="I" PHYSICAL="PLB_UABus"/><PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/><PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/><PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/><PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/><PORTMAP DIR="I" PHYSICAL="PLB_masterID"/><PORTMAP DIR="I" PHYSICAL="PLB_abort"/><PORTMAP DIR="I" PHYSICAL="PLB_busLock"/><PORTMAP DIR="I" PHYSICAL="PLB_RNW"/><PORTMAP DIR="I" PHYSICAL="PLB_BE"/><PORTMAP DIR="I" PHYSICAL="PLB_MSize"/><PORTMAP DIR="I" PHYSICAL="PLB_size"/><PORTMAP DIR="I" PHYSICAL="PLB_type"/><PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/><PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/><PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/><PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/><PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/><PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/><PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/><PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/><PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/><PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/><PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/><PORTMAP DIR="O" PHYSICAL="Sl_SSize"/><PORTMAP DIR="O" PHYSICAL="Sl_wait"/><PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/><PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/><PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/><PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/><PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/><PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/><PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/><PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/><PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/><PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/><PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/><PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/><PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="microblaze_0_mdm_bus" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="MBDEBUG_0" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="Dbg_Clk_0"/><PORTMAP DIR="O" PHYSICAL="Dbg_TDI_0"/><PORTMAP DIR="I" PHYSICAL="Dbg_TDO_0"/><PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_0"/><PORTMAP DIR="O" PHYSICAL="Dbg_Capture_0"/><PORTMAP DIR="O" PHYSICAL="Dbg_Shift_0"/><PORTMAP DIR="O" PHYSICAL="Dbg_Update_0"/><PORTMAP DIR="O" PHYSICAL="Dbg_Rst_0"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="3" NAME="MBDEBUG_1" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="Dbg_Clk_1"/><PORTMAP DIR="O" PHYSICAL="Dbg_TDI_1"/><PORTMAP DIR="I" PHYSICAL="Dbg_TDO_1"/><PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_1"/><PORTMAP DIR="O" PHYSICAL="Dbg_Capture_1"/><PORTMAP DIR="O" PHYSICAL="Dbg_Shift_1"/><PORTMAP DIR="O" PHYSICAL="Dbg_Update_1"/><PORTMAP DIR="O" PHYSICAL="Dbg_Rst_1"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="4" NAME="MBDEBUG_2" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="Dbg_Clk_2"/><PORTMAP DIR="O" PHYSICAL="Dbg_TDI_2"/><PORTMAP DIR="I" PHYSICAL="Dbg_TDO_2"/><PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_2"/><PORTMAP DIR="O" PHYSICAL="Dbg_Capture_2"/><PORTMAP DIR="O" PHYSICAL="Dbg_Shift_2"/><PORTMAP DIR="O" PHYSICAL="Dbg_Update_2"/><PORTMAP DIR="O" PHYSICAL="Dbg_Rst_2"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_3" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="Dbg_Clk_3"/><PORTMAP DIR="O" PHYSICAL="Dbg_TDI_3"/><PORTMAP DIR="I" PHYSICAL="Dbg_TDO_3"/><PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_3"/><PORTMAP DIR="O" PHYSICAL="Dbg_Capture_3"/><PORTMAP DIR="O" PHYSICAL="Dbg_Shift_3"/><PORTMAP DIR="O" PHYSICAL="Dbg_Update_3"/><PORTMAP DIR="O" PHYSICAL="Dbg_Rst_3"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_4" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="Dbg_Clk_4"/><PORTMAP DIR="O" PHYSICAL="Dbg_TDI_4"/><PORTMAP DIR="I" PHYSICAL="Dbg_TDO_4"/><PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_4"/><PORTMAP DIR="O" PHYSICAL="Dbg_Capture_4"/><PORTMAP DIR="O" PHYSICAL="Dbg_Shift_4"/><PORTMAP DIR="O" PHYSICAL="Dbg_Update_4"/><PORTMAP DIR="O" PHYSICAL="Dbg_Rst_4"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_5" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="Dbg_Clk_5"/><PORTMAP DIR="O" PHYSICAL="Dbg_TDI_5"/><PORTMAP DIR="I" PHYSICAL="Dbg_TDO_5"/><PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_5"/><PORTMAP DIR="O" PHYSICAL="Dbg_Capture_5"/><PORTMAP DIR="O" PHYSICAL="Dbg_Shift_5"/><PORTMAP DIR="O" PHYSICAL="Dbg_Update_5"/><PORTMAP DIR="O" PHYSICAL="Dbg_Rst_5"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_6" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="Dbg_Clk_6"/><PORTMAP DIR="O" PHYSICAL="Dbg_TDI_6"/><PORTMAP DIR="I" PHYSICAL="Dbg_TDO_6"/><PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_6"/><PORTMAP DIR="O" PHYSICAL="Dbg_Capture_6"/><PORTMAP DIR="O" PHYSICAL="Dbg_Shift_6"/><PORTMAP DIR="O" PHYSICAL="Dbg_Update_6"/><PORTMAP DIR="O" PHYSICAL="Dbg_Rst_6"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_7" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="Dbg_Clk_7"/><PORTMAP DIR="O" PHYSICAL="Dbg_TDI_7"/><PORTMAP DIR="I" PHYSICAL="Dbg_TDO_7"/><PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_7"/><PORTMAP DIR="O" PHYSICAL="Dbg_Capture_7"/><PORTMAP DIR="O" PHYSICAL="Dbg_Shift_7"/><PORTMAP DIR="O" PHYSICAL="Dbg_Update_7"/><PORTMAP DIR="O" PHYSICAL="Dbg_Rst_7"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="10" NAME="XMTC" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="O" PHYSICAL="Ext_JTAG_DRCK"/><PORTMAP DIR="O" PHYSICAL="Ext_JTAG_RESET"/><PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SEL"/><PORTMAP DIR="O" PHYSICAL="Ext_JTAG_CAPTURE"/><PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SHIFT"/><PORTMAP DIR="O" PHYSICAL="Ext_JTAG_UPDATE"/><PORTMAP DIR="O" PHYSICAL="Ext_JTAG_TDI"/><PORTMAP DIR="I" PHYSICAL="Ext_JTAG_TDO"/></PORTMAPS></BUSINTERFACE></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="2218786816" BASENAME="C_BASEADDR" BASEVALUE="0x84400000" HIGHDECIMAL="2218852351" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8440ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K"><SLAVES><SLAVE BUSINTERFACE="SPLB"/><SLAVE BUSINTERFACE="S_AXI"/></SLAVES></MEMRANGE></MEMORYMAP><RESOURCES><RESOURCE PERCENT="0" TOTAL="14752" TYPE="Slices" USED="95"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="Slice Flip Flops" USED="126"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="4 input LUTs" USED="148"/><RESOURCE PERCENT="NA" TOTAL="NA" TYPE="IOs" USED="489"/><RESOURCE PERCENT="0" TOTAL="250" TYPE="bonded IOBs" USED="0"/><RESOURCE PERCENT="8" TOTAL="24" TYPE="GCLKs" USED="2"/></RESOURCES><TIMING FREQUNITS="MHz" MAXFREQ="87.627"><TIMECLK SIGNAME="mdm_0/update"/><TIMECLK SIGNAME="SPLB_Clk"/><TIMECLK SIGNAME="mdm_0/drck_i"/></TIMING></MODULE><MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset"><DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION><DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="lx"><DESCRIPTION>Device Subfamily</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4"><DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4"><DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION></PARAMETER><PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1"><DESCRIPTION>External Reset Active High </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1"><DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1"><DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1"><DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1"><DESCRIPTION>Number of Active Low Interconnect Reset Registered Outputs </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1"><DESCRIPTION>Number of Active Low Peripheral Reset Registered Outputs </DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="spartan3e"><DESCRIPTION>Device Family</DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/><PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="sys_rst_s"/><PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="Debug_SYS_Rst"/><PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="Dcm_all_locked"/><PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="mb_reset"/><PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="18" NAME="Bus_Struct_Reset" SIGIS="RST" SIGNAME="sys_bus_reset" VECFORMULA="[0:C_NUM_BUS_RST-1]"/><PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="sys_periph_reset" VECFORMULA="[0:C_NUM_PERP_RST-1]"/><PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/><PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/><PORT DIR="O" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/><PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/><PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/><PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/><PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/><PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/><PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/></PORTMAPS></BUSINTERFACE><BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/><PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/><PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/><PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/><PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/><PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/></PORTMAPS></BUSINTERFACE></BUSINTERFACES><IOINTERFACES><IOINTERFACE MPD_INDEX="0" NAME="reset_0"/></IOINTERFACES><RESOURCES><RESOURCE PERCENT="0" TOTAL="14752" TYPE="Slices" USED="42"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="Slice Flip Flops" USED="69"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="4 input LUTs" USED="53"/><RESOURCE PERCENT="NA" TOTAL="NA" TYPE="IOs" USED="22"/><RESOURCE PERCENT="0" TOTAL="250" TYPE="bonded IOBs" USED="0"/></RESOURCES><TIMING FREQUNITS="MHz" MAXFREQ="198.531"><TIMECLK SIGNAME="Slowest_sync_clk"/></TIMING></MODULE><MODULE HWVERSION="2.01.a" INSTANCE="xps_intc_0" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="INTERRUPT_CNTLR" MODTYPE="xps_intc"><DESCRIPTION TYPE="SHORT">XPS Interrupt Controller</DESCRIPTION><DESCRIPTION TYPE="LONG">intc core attached to the PLBV46</DESCRIPTION><DOCUMENTATION><DOCUMENT SOURCE="C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_intc_v2_01_a/doc/xps_intc.pdf" TYPE="IP"/></DOCUMENTATION><LICENSEINFO ICON_NAME="ps_core_preferred"/><PARAMETERS><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e"><DESCRIPTION>Device Family</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="1" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x81800000"><DESCRIPTION>Base Address</DESCRIPTION></PARAMETER><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="2" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8180ffff"><DESCRIPTION>High Address</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="3" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>PLB Address Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="4" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>PLB Data Bus Width</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="5" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2"><DESCRIPTION>Number of PLB Masters</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="7" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="8" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"><DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="9" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"><DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="10" NAME="C_NUM_INTR_INPUTS" TYPE="INTEGER" VALUE="2"><DESCRIPTION>Number of Interrupt Inputs </DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_KIND_OF_INTR" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111110"><DESCRIPTION>Type of Interrupt for Each Input </DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_KIND_OF_EDGE" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111"><DESCRIPTION>Type of Each Edge Senstive Interrupt </DESCRIPTION></PARAMETER><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_KIND_OF_LVL" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111"><DESCRIPTION>Type of Each Level Sensitive Interrupt </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="14" NAME="C_HAS_IPR" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Support IPR </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="15" NAME="C_HAS_SIE" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Support SIE </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="16" NAME="C_HAS_CIE" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Support CIE </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="17" NAME="C_HAS_IVR" TYPE="INTEGER" VALUE="1"><DESCRIPTION>Support IVR </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="18" NAME="C_IRQ_IS_LEVEL" TYPE="INTEGER" VALUE="1"><DESCRIPTION>IRQ Output Use Level </DESCRIPTION></PARAMETER><PARAMETER MPD_INDEX="19" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1"><DESCRIPTION>The Sense of IRQ Output </DESCRIPTION></PARAMETER></PARAMETERS><PORTS><PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="0" MPD_INDEX="42" MSB="1" NAME="Intr" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_DCE_Interrupt & uart_plb_0_IP2INTC_Irpt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]"><SIGNALS><SIGNAL NAME="RS232_DCE_Interrupt"/><SIGNAL NAME="uart_plb_0_IP2INTC_Irpt"/></SIGNALS></PORT><PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="43" NAME="Irq" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="microblaze_0_Interrupt"/><PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="3" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" MPD_INDEX="4" NAME="PLB_masterID" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="5" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="6" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="8" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="10" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="11" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="12" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="13" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="14" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="15" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="16" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="17" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="33" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="34" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="35" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="37" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="38" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="40" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/><PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/><PORTMAP DIR="I" PHYSICAL="PLB_ABus"/><PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/><PORTMAP DIR="I" PHYSICAL="PLB_masterID"/><PORTMAP DIR="I" PHYSICAL="PLB_RNW"/><PORTMAP DIR="I" PHYSICAL="PLB_BE"/><PORTMAP DIR="I" PHYSICAL="PLB_size"/><PORTMAP DIR="I" PHYSICAL="PLB_type"/><PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/><PORTMAP DIR="I" PHYSICAL="PLB_UABus"/><PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/><PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/><PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/><PORTMAP DIR="I" PHYSICAL="PLB_abort"/><PORTMAP DIR="I" PHYSICAL="PLB_busLock"/><PORTMAP DIR="I" PHYSICAL="PLB_MSize"/><PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/><PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/><PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/><PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/><PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/><PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/><PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/><PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/><PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/><PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/><PORTMAP DIR="O" PHYSICAL="Sl_SSize"/><PORTMAP DIR="O" PHYSICAL="Sl_wait"/><PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/><PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/><PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/><PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/><PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/><PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/><PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/><PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/><PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/><PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/><PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/><PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/><PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/></PORTMAPS></BUSINTERFACE></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="2172649472" BASENAME="C_BASEADDR" BASEVALUE="0x81800000" HIGHDECIMAL="2172715007" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8180ffff" MEMTYPE="REGISTER" MINSIZE="0x20" SIZE="65536" SIZEABRV="64K"><SLAVES><SLAVE BUSINTERFACE="SPLB"/></SLAVES></MEMRANGE></MEMORYMAP><INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER"><SOURCE INSTANCE="RS232_DCE" PRIORITY="0" SIGNAME="RS232_DCE_Interrupt"/><SOURCE INSTANCE="uart_plb_0" PRIORITY="1" SIGNAME="uart_plb_0_IP2INTC_Irpt"/><TARGET INSTANCE="microblaze_0"/></INTERRUPTINFO><RESOURCES><RESOURCE PERCENT="0" TOTAL="14752" TYPE="Slices" USED="91"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="Slice Flip Flops" USED="128"/><RESOURCE PERCENT="0" TOTAL="29504" TYPE="4 input LUTs" USED="96"/><RESOURCE PERCENT="NA" TOTAL="NA" TYPE="IOs" USED="204"/><RESOURCE PERCENT="0" TOTAL="250" TYPE="bonded IOBs" USED="0"/></RESOURCES><TIMING FREQUNITS="MHz" MAXFREQ="199.960"><TIMECLK SIGNAME="SPLB_Clk"/><TIMECLK SIGNAME="Intr<1>"/></TIMING></MODULE><MODULE HWVERSION="1.00.a" INSTANCE="uart_plb_0" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="uart_plb"><LICENSEINFO ICON_NAME="ps_core_local"/><PARAMETERS><PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0xcd000000"/><PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0xcd00ffff"/><PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"/><PARAMETER MPD_INDEX="6" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/><PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/><PARAMETER MPD_INDEX="9" NAME="C_SPLB_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_SPLB_CLK_PERIOD_PS" TYPE="INTEGER" VALUE="20000"/><PARAMETER MPD_INDEX="11" NAME="C_INCLUDE_DPHASE_TIMER" TYPE="INTEGER" VALUE="0"/><PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e"/></PARAMETERS><PORTS><PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="tx_sout" SIGNAME="uart_plb_0_tx_sout"/><PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="rx_sin" SIGNAME="uart_plb_0_rx_sin"/><PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="44" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="uart_plb_0_IP2INTC_Irpt"/><PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="2" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="3" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="6" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="7" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="8" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="9" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" MPD_INDEX="10" NAME="PLB_masterID" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="11" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="12" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="13" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="15" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="17" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="18" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="20" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="21" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="22" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="23" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="25" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="26" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="27" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="28" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="29" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="30" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="31" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="32" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="33" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="34" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="36" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="37" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="38" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="39" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="40" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="42" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/><PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="43" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/></PORTS><BUSINTERFACES><BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"><PORTMAPS><PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/><PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/><PORTMAP DIR="I" PHYSICAL="PLB_ABus"/><PORTMAP DIR="I" PHYSICAL="PLB_UABus"/><PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/><PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/><PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/><PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/><PORTMAP DIR="I" PHYSICAL="PLB_masterID"/><PORTMAP DIR="I" PHYSICAL="PLB_abort"/><PORTMAP DIR="I" PHYSICAL="PLB_busLock"/><PORTMAP DIR="I" PHYSICAL="PLB_RNW"/><PORTMAP DIR="I" PHYSICAL="PLB_BE"/><PORTMAP DIR="I" PHYSICAL="PLB_MSize"/><PORTMAP DIR="I" PHYSICAL="PLB_size"/><PORTMAP DIR="I" PHYSICAL="PLB_type"/><PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/><PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/><PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/><PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/><PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/><PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/><PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/><PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/><PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/><PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/><PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/><PORTMAP DIR="O" PHYSICAL="Sl_SSize"/><PORTMAP DIR="O" PHYSICAL="Sl_wait"/><PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/><PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/><PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/><PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/><PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/><PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/><PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/><PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/><PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/><PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/><PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/><PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/><PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/></PORTMAPS></BUSINTERFACE></BUSINTERFACES><MEMORYMAP><MEMRANGE BASEDECIMAL="3439329280" BASENAME="C_BASEADDR" BASEVALUE="0xcd000000" HIGHDECIMAL="3439394815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xcd00ffff" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"><SLAVES><SLAVE BUSINTERFACE="SPLB"/></SLAVES></MEMRANGE></MEMORYMAP><INTERRUPTINFO TYPE="SOURCE"><TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="1"/></INTERRUPTINFO><RESOURCES><RESOURCE PERCENT="2" TOTAL="14752" TYPE="Slices" USED="433"/><RESOURCE PERCENT="1" TOTAL="29504" TYPE="Slice Flip Flops" USED="519"/><RESOURCE PERCENT="1" TOTAL="29504" TYPE="4 input LUTs" USED="537"/><RESOURCE PERCENT="NA" TOTAL="NA" TYPE="IOs" USED="204"/><RESOURCE PERCENT="0" TOTAL="250" TYPE="bonded IOBs" USED="0"/><RESOURCE PERCENT="5" TOTAL="36" TYPE="BRAMs" USED="2"/></RESOURCES><TIMING FREQUNITS="MHz" MAXFREQ="132.066"><TIMECLK SIGNAME="SPLB_Clk"/></TIMING></MODULE></MODULES></EDKSYSTEM>