URL
https://opencores.org/ocsvn/uart_plb/uart_plb/trunk
Subversion Repositories uart_plb
[/] [uart_plb/] [trunk/] [pcores/] [uart_plb_v1_00_a/] [data/] [_uart_plb_xst.prj] - Rev 2
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vhdl proc_common_v3_00_a "C:\Xilinx\13.1\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd"vhdl proc_common_v3_00_a "C:\Xilinx\13.1\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd"vhdl proc_common_v3_00_a "C:\Xilinx\13.1\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd"vhdl proc_common_v3_00_a "C:\Xilinx\13.1\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd"vhdl proc_common_v3_00_a "C:\Xilinx\13.1\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd"vhdl proc_common_v3_00_a "C:\Xilinx\13.1\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd"vhdl proc_common_v3_00_a "C:\Xilinx\13.1\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd"vhdl plbv46_slave_single_v1_01_a "C:\Xilinx\13.1\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_address_decoder.vhd"vhdl plbv46_slave_single_v1_01_a "C:\Xilinx\13.1\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd"vhdl plbv46_slave_single_v1_01_a "C:\Xilinx\13.1\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plbv46_slave_single.vhd"vhdl interrupt_control_v2_01_a "C:\Xilinx\13.1\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd"vhdl uart_plb_v1_00_a "../hdl/vhdl/user_logic.vhd"vhdl uart_plb_v1_00_a "../hdl/vhdl/uart_plb.vhd"