Subversion Repositories uart_plb

INFO:EDK:3186 - hierarchical library inclusion detected, all file(s) of library
   proc_common_v3_00_a will be used ...
INFO:EDK:3186 - hierarchical library inclusion detected, all file(s) of library
   plbv46_slave_single_v1_01_a will be used ...
INFO:EDK:3186 - hierarchical library inclusion detected, all file(s) of library
   interrupt_control_v2_01_a will be used ...
Parsing PAO project file successfully ...
Analyzing HDL source files ...
WARNING:EDK:1303 - Failed to infer sub library HDL file uart_components.vhd from
   reference repositories!
   Either add more reference repositories or skip this sub library file ...
INFO:EDK:3186 - hierarchical library inclusion detected, all file(s) of library
   proc_common_v3_00_a will be used ...
INFO:EDK:3186 - hierarchical library inclusion detected, all file(s) of library
   plbv46_slave_single_v1_01_a will be used ...
INFO:EDK:3186 - hierarchical library inclusion detected, all file(s) of library
   interrupt_control_v2_01_a will be used ...
Parsing PAO project file successfully ...
Analyzing HDL source files ...
Analyzing HDL source files successfully ...
HDL language for the peripheral (top level) design unit uart_plb is vhdl ...
resolving hierarchical inclusion of library proc_common_v3_00_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
resolving hierarchical inclusion of library plbv46_slave_single_v1_01_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
resolving hierarchical inclusion of library interrupt_control_v2_01_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
INFO:EDK:3391 - Create temporary xst project file:
   C:\uart_plb\pcores/uart_plb.prj
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/inferred_lut4.vhd" in Library proc_common_v3_00_a.
Entity <inferred_lut4> compiled.
Entity <inferred_lut4> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/muxf_struct_f.vhd" in Library proc_common_v3_00_a.
Entity <muxf_struct> compiled.
Entity <muxf_struct> (Architecture <imp>) compiled.
Entity <muxf_struct_f> compiled.
Entity <muxf_struct_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_bit> compiled.
Entity <pf_counter_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/cntr_incr_decr_addn_f.vhd" in Library proc_common_v3_00_a.
Entity <cntr_incr_decr_addn_f> compiled.
Entity <cntr_incr_decr_addn_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/dynshreg_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_f> compiled.
Entity <dynshreg_f> (Architecture <behavioral>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_adder_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder_bit> compiled.
Entity <pf_adder_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter> compiled.
Entity <pf_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_occ_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter> compiled.
Entity <pf_occ_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <counter_bit> compiled.
Entity <counter_bit> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy_f.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy_f> compiled.
Entity <or_muxcy_f> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_rbu_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu_f> compiled.
Entity <srl_fifo_rbu_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family.vhd" in Library proc_common_v3_00_a.
Package <family> compiled.
Package body <family> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_occ_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter_top> compiled.
Entity <pf_occ_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_top> compiled.
Entity <pf_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_adder.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder> compiled.
Entity <pf_adder> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter.vhd" in Library proc_common_v3_00_a.
Entity <Counter> compiled.
Entity <Counter> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/coregen_comp_defs.vhd" in Library proc_common_v3_00_a.
Package <coregen_comp_defs> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/common_types_pkg.vhd" in Library proc_common_v3_00_a.
Package <Common_Types> compiled.
Package body <Common_Types> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/conv_funs_pkg.vhd" in Library proc_common_v3_00_a.
Package <conv_funs_pkg> compiled.
Package body <conv_funs_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/async_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <async_fifo_fg> compiled.
Entity <async_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/sync_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <sync_fifo_fg> compiled.
Entity <sync_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/blk_mem_gen_wrapper.vhd" in Library proc_common_v3_00_a.
Entity <blk_mem_gen_wrapper> compiled.
Entity <blk_mem_gen_wrapper> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/addsub.vhd" in Library proc_common_v3_00_a.
Entity <addsub> compiled.
Entity <addsub> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/direct_path_cntr.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr> compiled.
Entity <direct_path_cntr> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/direct_path_cntr_ai.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr_ai> compiled.
Entity <direct_path_cntr_ai> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/down_counter.vhd" in Library proc_common_v3_00_a.
Entity <down_counter> compiled.
Entity <down_counter> (Architecture <simulation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/eval_timer.vhd" in Library proc_common_v3_00_a.
Entity <eval_timer> compiled.
Entity <eval_timer> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_steer.vhd" in Library proc_common_v3_00_a.
Entity <IPIF_Steer> compiled.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_steer128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_steer128> compiled.
Entity <ipif_steer128> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_mirror128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_mirror128> compiled.
Entity <ipif_mirror128> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ld_arith_reg.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg> compiled.
Entity <ld_arith_reg> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ld_arith_reg2.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg2> compiled.
Entity <ld_arith_reg2> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/mux_onehot.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot> compiled.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_bits.vhd" in Library proc_common_v3_00_a.
Entity <or_bits> compiled.
Entity <or_bits> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate.vhd" in Library proc_common_v3_00_a.
Entity <or_gate> compiled.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_dpram_select.vhd" in Library proc_common_v3_00_a.
Entity <pf_dpram_select> compiled.
Entity <pf_dpram_select> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect.vhd" in Library proc_common_v3_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_mask.vhd" in Library proc_common_v3_00_a.
Entity <pselect_mask> compiled.
Entity <pselect_mask> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl16_fifo.vhd" in Library proc_common_v3_00_a.
Entity <srl16_fifo> compiled.
Entity <srl16_fifo> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo.vhd" in Library proc_common_v3_00_a.
Entity <SRL_FIFO> compiled.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo2.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo2> compiled.
Entity <srl_fifo2> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo3.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo3> compiled.
Entity <srl_fifo3> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_rbu.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu> compiled.
Entity <srl_fifo_rbu> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/valid_be.vhd" in Library proc_common_v3_00_a.
Entity <valid_be> compiled.
Entity <valid_be> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_with_enable_f.vhd" in Library proc_common_v3_00_a.
Entity <or_with_enable_f> compiled.
Entity <or_with_enable_f> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/dynshreg_i_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_i_f> compiled.
Entity <dynshreg_i_f> (Architecture <behavioral>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/mux_onehot_f.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot_f> compiled.
Entity <mux_onehot_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_f> compiled.
Entity <srl_fifo_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/compare_vectors_f.vhd" in Library proc_common_v3_00_a.
Entity <compare_vectors_f> compiled.
Entity <compare_vectors_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate_f.vhd" in Library proc_common_v3_00_a.
Entity <or_gate_f> compiled.
Entity <or_gate_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/soft_reset.vhd" in Library proc_common_v3_00_a.
Entity <soft_reset> compiled.
Entity <soft_reset> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_components.vhd" in Library
uart_plb_v1_00_a.
Package <uart_components> compiled.
Package body <uart_components> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/baud.vhd" in
Library uart_plb_v1_00_a.
Entity <baudrate> compiled.
Entity <baudrate> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/tx.vhd" in
Library uart_plb_v1_00_a.
Entity <xmt> compiled.
Entity <xmt> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/fifo_generator_v8_1_8x16.vhd" in
Library uart_plb_v1_00_a.
Entity <fifo_generator_v8_1_8x16> compiled.
Entity <fifo_generator_v8_1_8x16> (Architecture <fifo_generator_v8_1_8x16_a>)
compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/tmo.vhd" in
Library uart_plb_v1_00_a.
Entity <tmo> compiled.
Entity <tmo> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/rx.vhd" in
Library uart_plb_v1_00_a.
Entity <rcv> compiled.
Entity <rcv> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_0
1_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.
Entity <interrupt_control> compiled.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plbv46_slave_single> compiled.
Entity <plbv46_slave_single> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/user_logic.vhd" in Library
uart_plb_v1_00_a.
Entity <user_logic> compiled.
ERROR:HDLParsers:3312 -
   "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/user_logic.vhd" Line 160.
   Undefined symbol 'uart_plb_ip'.
ERROR:EDK:2121 - Parse Errors encountered in HDL source
WARNING:EDK:3590 - Unable to delete temporary project file
   C:\uart_plb\pcores\uart_plb.prj : 13
HDL language for the peripheral (top level) design unit uart_plb is vhdl ...
WARNING:EDK:2221 - Project file C:\uart_plb\pcores/uart_plb.prj already exists,
   will be overwrite and removed afterward ...
resolving hierarchical inclusion of library proc_common_v3_00_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
resolving hierarchical inclusion of library plbv46_slave_single_v1_01_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
resolving hierarchical inclusion of library interrupt_control_v2_01_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
INFO:EDK:3391 - Create temporary xst project file:
   C:\uart_plb\pcores/uart_plb.prj
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/inferred_lut4.vhd" in Library proc_common_v3_00_a.
Entity <inferred_lut4> compiled.
Entity <inferred_lut4> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/muxf_struct_f.vhd" in Library proc_common_v3_00_a.
Entity <muxf_struct> compiled.
Entity <muxf_struct> (Architecture <imp>) compiled.
Entity <muxf_struct_f> compiled.
Entity <muxf_struct_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_bit> compiled.
Entity <pf_counter_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/cntr_incr_decr_addn_f.vhd" in Library proc_common_v3_00_a.
Entity <cntr_incr_decr_addn_f> compiled.
Entity <cntr_incr_decr_addn_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/dynshreg_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_f> compiled.
Entity <dynshreg_f> (Architecture <behavioral>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_adder_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder_bit> compiled.
Entity <pf_adder_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter> compiled.
Entity <pf_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_occ_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter> compiled.
Entity <pf_occ_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <counter_bit> compiled.
Entity <counter_bit> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy_f.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy_f> compiled.
Entity <or_muxcy_f> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_rbu_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu_f> compiled.
Entity <srl_fifo_rbu_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family.vhd" in Library proc_common_v3_00_a.
Package <family> compiled.
Package body <family> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_occ_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter_top> compiled.
Entity <pf_occ_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_top> compiled.
Entity <pf_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_adder.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder> compiled.
Entity <pf_adder> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter.vhd" in Library proc_common_v3_00_a.
Entity <Counter> compiled.
Entity <Counter> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/coregen_comp_defs.vhd" in Library proc_common_v3_00_a.
Package <coregen_comp_defs> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/common_types_pkg.vhd" in Library proc_common_v3_00_a.
Package <Common_Types> compiled.
Package body <Common_Types> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/conv_funs_pkg.vhd" in Library proc_common_v3_00_a.
Package <conv_funs_pkg> compiled.
Package body <conv_funs_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/async_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <async_fifo_fg> compiled.
Entity <async_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/sync_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <sync_fifo_fg> compiled.
Entity <sync_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/blk_mem_gen_wrapper.vhd" in Library proc_common_v3_00_a.
Entity <blk_mem_gen_wrapper> compiled.
Entity <blk_mem_gen_wrapper> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/addsub.vhd" in Library proc_common_v3_00_a.
Entity <addsub> compiled.
Entity <addsub> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/direct_path_cntr.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr> compiled.
Entity <direct_path_cntr> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/direct_path_cntr_ai.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr_ai> compiled.
Entity <direct_path_cntr_ai> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/down_counter.vhd" in Library proc_common_v3_00_a.
Entity <down_counter> compiled.
Entity <down_counter> (Architecture <simulation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/eval_timer.vhd" in Library proc_common_v3_00_a.
Entity <eval_timer> compiled.
Entity <eval_timer> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_steer.vhd" in Library proc_common_v3_00_a.
Entity <IPIF_Steer> compiled.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_steer128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_steer128> compiled.
Entity <ipif_steer128> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_mirror128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_mirror128> compiled.
Entity <ipif_mirror128> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ld_arith_reg.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg> compiled.
Entity <ld_arith_reg> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ld_arith_reg2.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg2> compiled.
Entity <ld_arith_reg2> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/mux_onehot.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot> compiled.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_bits.vhd" in Library proc_common_v3_00_a.
Entity <or_bits> compiled.
Entity <or_bits> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate.vhd" in Library proc_common_v3_00_a.
Entity <or_gate> compiled.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_dpram_select.vhd" in Library proc_common_v3_00_a.
Entity <pf_dpram_select> compiled.
Entity <pf_dpram_select> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect.vhd" in Library proc_common_v3_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_mask.vhd" in Library proc_common_v3_00_a.
Entity <pselect_mask> compiled.
Entity <pselect_mask> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl16_fifo.vhd" in Library proc_common_v3_00_a.
Entity <srl16_fifo> compiled.
Entity <srl16_fifo> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo.vhd" in Library proc_common_v3_00_a.
Entity <SRL_FIFO> compiled.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo2.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo2> compiled.
Entity <srl_fifo2> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo3.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo3> compiled.
Entity <srl_fifo3> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_rbu.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu> compiled.
Entity <srl_fifo_rbu> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/valid_be.vhd" in Library proc_common_v3_00_a.
Entity <valid_be> compiled.
Entity <valid_be> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_with_enable_f.vhd" in Library proc_common_v3_00_a.
Entity <or_with_enable_f> compiled.
Entity <or_with_enable_f> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/dynshreg_i_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_i_f> compiled.
Entity <dynshreg_i_f> (Architecture <behavioral>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/mux_onehot_f.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot_f> compiled.
Entity <mux_onehot_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_f> compiled.
Entity <srl_fifo_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/compare_vectors_f.vhd" in Library proc_common_v3_00_a.
Entity <compare_vectors_f> compiled.
Entity <compare_vectors_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate_f.vhd" in Library proc_common_v3_00_a.
Entity <or_gate_f> compiled.
Entity <or_gate_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/soft_reset.vhd" in Library proc_common_v3_00_a.
Entity <soft_reset> compiled.
Entity <soft_reset> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_components.vhd" in Library
uart_plb_v1_00_a.
Package <uart_components> compiled.
Package body <uart_components> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_0
1_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.
Entity <interrupt_control> compiled.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plbv46_slave_single> compiled.
Entity <plbv46_slave_single> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/baud.vhd" in
Library uart_plb_v1_00_a.
Entity <baudrate> compiled.
Entity <baudrate> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/tx.vhd" in
Library uart_plb_v1_00_a.
Entity <xmt> compiled.
Entity <xmt> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/fifo_generator_v8_1_8x16.vhd" in
Library uart_plb_v1_00_a.
Entity <fifo_generator_v8_1_8x16> compiled.
Entity <fifo_generator_v8_1_8x16> (Architecture <fifo_generator_v8_1_8x16_a>)
compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/tmo.vhd" in
Library uart_plb_v1_00_a.
Entity <tmo> compiled.
Entity <tmo> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/rx.vhd" in
Library uart_plb_v1_00_a.
Entity <rcv> compiled.
Entity <rcv> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_plb.vhd"
in Library uart_plb_v1_00_a.
ERROR:HDLParsers:3014 -
   "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_plb.vhd" Line 76. Library
   unit user_logic is not available in library uart_plb_v1_00_a.
ERROR:EDK:2121 - Parse Errors encountered in HDL source
WARNING:EDK:3590 - Unable to delete temporary project file
   C:\uart_plb\pcores\uart_plb.prj : 13
INFO:EDK:3186 - hierarchical library inclusion detected, all file(s) of library
   proc_common_v3_00_a will be used ...
INFO:EDK:3186 - hierarchical library inclusion detected, all file(s) of library
   plbv46_slave_single_v1_01_a will be used ...
INFO:EDK:3186 - hierarchical library inclusion detected, all file(s) of library
   interrupt_control_v2_01_a will be used ...
Parsing PAO project file successfully ...
Analyzing HDL source files ...
Analyzing HDL source files successfully ...
HDL language for the peripheral (top level) design unit uart_plb is vhdl ...
WARNING:EDK:2221 - Project file C:\uart_plb\pcores/uart_plb.prj already exists,
   will be overwrite and removed afterward ...
resolving hierarchical inclusion of library proc_common_v3_00_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
resolving hierarchical inclusion of library plbv46_slave_single_v1_01_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
resolving hierarchical inclusion of library interrupt_control_v2_01_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
INFO:EDK:3391 - Create temporary xst project file:
   C:\uart_plb\pcores/uart_plb.prj
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/inferred_lut4.vhd" in Library proc_common_v3_00_a.
Entity <inferred_lut4> compiled.
Entity <inferred_lut4> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/muxf_struct_f.vhd" in Library proc_common_v3_00_a.
Entity <muxf_struct> compiled.
Entity <muxf_struct> (Architecture <imp>) compiled.
Entity <muxf_struct_f> compiled.
Entity <muxf_struct_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_bit> compiled.
Entity <pf_counter_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/cntr_incr_decr_addn_f.vhd" in Library proc_common_v3_00_a.
Entity <cntr_incr_decr_addn_f> compiled.
Entity <cntr_incr_decr_addn_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/dynshreg_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_f> compiled.
Entity <dynshreg_f> (Architecture <behavioral>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_adder_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder_bit> compiled.
Entity <pf_adder_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter> compiled.
Entity <pf_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_occ_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter> compiled.
Entity <pf_occ_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <counter_bit> compiled.
Entity <counter_bit> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy_f.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy_f> compiled.
Entity <or_muxcy_f> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_rbu_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu_f> compiled.
Entity <srl_fifo_rbu_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family.vhd" in Library proc_common_v3_00_a.
Package <family> compiled.
Package body <family> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_occ_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter_top> compiled.
Entity <pf_occ_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_top> compiled.
Entity <pf_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_adder.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder> compiled.
Entity <pf_adder> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter.vhd" in Library proc_common_v3_00_a.
Entity <Counter> compiled.
Entity <Counter> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/coregen_comp_defs.vhd" in Library proc_common_v3_00_a.
Package <coregen_comp_defs> compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_components.vhd" in Library
uart_plb_v1_00_a.
Package <uart_components> compiled.
Package body <uart_components> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/common_types_pkg.vhd" in Library proc_common_v3_00_a.
Package <Common_Types> compiled.
Package body <Common_Types> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/conv_funs_pkg.vhd" in Library proc_common_v3_00_a.
Package <conv_funs_pkg> compiled.
Package body <conv_funs_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/async_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <async_fifo_fg> compiled.
Entity <async_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/sync_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <sync_fifo_fg> compiled.
Entity <sync_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/blk_mem_gen_wrapper.vhd" in Library proc_common_v3_00_a.
Entity <blk_mem_gen_wrapper> compiled.
Entity <blk_mem_gen_wrapper> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/addsub.vhd" in Library proc_common_v3_00_a.
Entity <addsub> compiled.
Entity <addsub> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/direct_path_cntr.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr> compiled.
Entity <direct_path_cntr> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/direct_path_cntr_ai.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr_ai> compiled.
Entity <direct_path_cntr_ai> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/down_counter.vhd" in Library proc_common_v3_00_a.
Entity <down_counter> compiled.
Entity <down_counter> (Architecture <simulation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/eval_timer.vhd" in Library proc_common_v3_00_a.
Entity <eval_timer> compiled.
Entity <eval_timer> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_steer.vhd" in Library proc_common_v3_00_a.
Entity <IPIF_Steer> compiled.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_steer128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_steer128> compiled.
Entity <ipif_steer128> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_mirror128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_mirror128> compiled.
Entity <ipif_mirror128> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ld_arith_reg.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg> compiled.
Entity <ld_arith_reg> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ld_arith_reg2.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg2> compiled.
Entity <ld_arith_reg2> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/mux_onehot.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot> compiled.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_bits.vhd" in Library proc_common_v3_00_a.
Entity <or_bits> compiled.
Entity <or_bits> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate.vhd" in Library proc_common_v3_00_a.
Entity <or_gate> compiled.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_dpram_select.vhd" in Library proc_common_v3_00_a.
Entity <pf_dpram_select> compiled.
Entity <pf_dpram_select> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect.vhd" in Library proc_common_v3_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_mask.vhd" in Library proc_common_v3_00_a.
Entity <pselect_mask> compiled.
Entity <pselect_mask> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl16_fifo.vhd" in Library proc_common_v3_00_a.
Entity <srl16_fifo> compiled.
Entity <srl16_fifo> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo.vhd" in Library proc_common_v3_00_a.
Entity <SRL_FIFO> compiled.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo2.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo2> compiled.
Entity <srl_fifo2> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo3.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo3> compiled.
Entity <srl_fifo3> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_rbu.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu> compiled.
Entity <srl_fifo_rbu> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/valid_be.vhd" in Library proc_common_v3_00_a.
Entity <valid_be> compiled.
Entity <valid_be> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_with_enable_f.vhd" in Library proc_common_v3_00_a.
Entity <or_with_enable_f> compiled.
Entity <or_with_enable_f> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/dynshreg_i_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_i_f> compiled.
Entity <dynshreg_i_f> (Architecture <behavioral>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/mux_onehot_f.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot_f> compiled.
Entity <mux_onehot_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_f> compiled.
Entity <srl_fifo_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/compare_vectors_f.vhd" in Library proc_common_v3_00_a.
Entity <compare_vectors_f> compiled.
Entity <compare_vectors_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate_f.vhd" in Library proc_common_v3_00_a.
Entity <or_gate_f> compiled.
Entity <or_gate_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/soft_reset.vhd" in Library proc_common_v3_00_a.
Entity <soft_reset> compiled.
Entity <soft_reset> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/baud.vhd" in
Library uart_plb_v1_00_a.
Entity <baudrate> compiled.
Entity <baudrate> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/tx.vhd" in
Library uart_plb_v1_00_a.
Entity <xmt> compiled.
Entity <xmt> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/fifo_generator_v8_1_8x16.vhd" in
Library uart_plb_v1_00_a.
Entity <fifo_generator_v8_1_8x16> compiled.
Entity <fifo_generator_v8_1_8x16> (Architecture <fifo_generator_v8_1_8x16_a>)
compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/tmo.vhd" in
Library uart_plb_v1_00_a.
Entity <tmo> compiled.
Entity <tmo> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/rx.vhd" in
Library uart_plb_v1_00_a.
Entity <rcv> compiled.
Entity <rcv> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart.vhd" in
Library uart_plb_v1_00_a.
Entity <uart> compiled.
Entity <uart> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_0
1_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.
Entity <interrupt_control> compiled.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plbv46_slave_single> compiled.
Entity <plbv46_slave_single> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/user_logic.vhd" in Library
uart_plb_v1_00_a.
Entity <user_logic> compiled.
Entity <user_logic> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_plb.vhd"
in Library uart_plb_v1_00_a.
Entity <uart_plb> compiled.
ERROR:HDLParsers:851 -
   "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_plb.vhd" Line 476. Formal
   rx_sin of entity with no default value must be associated with an actual
   value.
ERROR:EDK:2121 - Parse Errors encountered in HDL source
WARNING:EDK:3590 - Unable to delete temporary project file
   C:\uart_plb\pcores\uart_plb.prj : 13
HDL language for the peripheral (top level) design unit uart_plb is vhdl ...
WARNING:EDK:2221 - Project file C:\uart_plb\pcores/uart_plb.prj already exists,
   will be overwrite and removed afterward ...
resolving hierarchical inclusion of library proc_common_v3_00_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
resolving hierarchical inclusion of library plbv46_slave_single_v1_01_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
resolving hierarchical inclusion of library interrupt_control_v2_01_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
INFO:EDK:3391 - Create temporary xst project file:
   C:\uart_plb\pcores/uart_plb.prj
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/inferred_lut4.vhd" in Library proc_common_v3_00_a.
Entity <inferred_lut4> compiled.
Entity <inferred_lut4> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/muxf_struct_f.vhd" in Library proc_common_v3_00_a.
Entity <muxf_struct> compiled.
Entity <muxf_struct> (Architecture <imp>) compiled.
Entity <muxf_struct_f> compiled.
Entity <muxf_struct_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_bit> compiled.
Entity <pf_counter_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/cntr_incr_decr_addn_f.vhd" in Library proc_common_v3_00_a.
Entity <cntr_incr_decr_addn_f> compiled.
Entity <cntr_incr_decr_addn_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/dynshreg_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_f> compiled.
Entity <dynshreg_f> (Architecture <behavioral>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_adder_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder_bit> compiled.
Entity <pf_adder_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter> compiled.
Entity <pf_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_occ_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter> compiled.
Entity <pf_occ_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <counter_bit> compiled.
Entity <counter_bit> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy_f.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy_f> compiled.
Entity <or_muxcy_f> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_rbu_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu_f> compiled.
Entity <srl_fifo_rbu_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family.vhd" in Library proc_common_v3_00_a.
Package <family> compiled.
Package body <family> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_occ_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter_top> compiled.
Entity <pf_occ_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_top> compiled.
Entity <pf_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_adder.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder> compiled.
Entity <pf_adder> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter.vhd" in Library proc_common_v3_00_a.
Entity <Counter> compiled.
Entity <Counter> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/coregen_comp_defs.vhd" in Library proc_common_v3_00_a.
Package <coregen_comp_defs> compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_components.vhd" in Library
uart_plb_v1_00_a.
Package <uart_components> compiled.
Package body <uart_components> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/common_types_pkg.vhd" in Library proc_common_v3_00_a.
Package <Common_Types> compiled.
Package body <Common_Types> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/conv_funs_pkg.vhd" in Library proc_common_v3_00_a.
Package <conv_funs_pkg> compiled.
Package body <conv_funs_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/async_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <async_fifo_fg> compiled.
Entity <async_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/sync_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <sync_fifo_fg> compiled.
Entity <sync_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/blk_mem_gen_wrapper.vhd" in Library proc_common_v3_00_a.
Entity <blk_mem_gen_wrapper> compiled.
Entity <blk_mem_gen_wrapper> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/addsub.vhd" in Library proc_common_v3_00_a.
Entity <addsub> compiled.
Entity <addsub> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/direct_path_cntr.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr> compiled.
Entity <direct_path_cntr> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/direct_path_cntr_ai.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr_ai> compiled.
Entity <direct_path_cntr_ai> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/down_counter.vhd" in Library proc_common_v3_00_a.
Entity <down_counter> compiled.
Entity <down_counter> (Architecture <simulation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/eval_timer.vhd" in Library proc_common_v3_00_a.
Entity <eval_timer> compiled.
Entity <eval_timer> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_steer.vhd" in Library proc_common_v3_00_a.
Entity <IPIF_Steer> compiled.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_steer128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_steer128> compiled.
Entity <ipif_steer128> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_mirror128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_mirror128> compiled.
Entity <ipif_mirror128> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ld_arith_reg.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg> compiled.
Entity <ld_arith_reg> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ld_arith_reg2.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg2> compiled.
Entity <ld_arith_reg2> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/mux_onehot.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot> compiled.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_bits.vhd" in Library proc_common_v3_00_a.
Entity <or_bits> compiled.
Entity <or_bits> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate.vhd" in Library proc_common_v3_00_a.
Entity <or_gate> compiled.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_dpram_select.vhd" in Library proc_common_v3_00_a.
Entity <pf_dpram_select> compiled.
Entity <pf_dpram_select> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect.vhd" in Library proc_common_v3_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_mask.vhd" in Library proc_common_v3_00_a.
Entity <pselect_mask> compiled.
Entity <pselect_mask> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl16_fifo.vhd" in Library proc_common_v3_00_a.
Entity <srl16_fifo> compiled.
Entity <srl16_fifo> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo.vhd" in Library proc_common_v3_00_a.
Entity <SRL_FIFO> compiled.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo2.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo2> compiled.
Entity <srl_fifo2> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo3.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo3> compiled.
Entity <srl_fifo3> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_rbu.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu> compiled.
Entity <srl_fifo_rbu> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/valid_be.vhd" in Library proc_common_v3_00_a.
Entity <valid_be> compiled.
Entity <valid_be> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_with_enable_f.vhd" in Library proc_common_v3_00_a.
Entity <or_with_enable_f> compiled.
Entity <or_with_enable_f> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/dynshreg_i_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_i_f> compiled.
Entity <dynshreg_i_f> (Architecture <behavioral>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/mux_onehot_f.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot_f> compiled.
Entity <mux_onehot_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_f> compiled.
Entity <srl_fifo_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/compare_vectors_f.vhd" in Library proc_common_v3_00_a.
Entity <compare_vectors_f> compiled.
Entity <compare_vectors_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate_f.vhd" in Library proc_common_v3_00_a.
Entity <or_gate_f> compiled.
Entity <or_gate_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/soft_reset.vhd" in Library proc_common_v3_00_a.
Entity <soft_reset> compiled.
Entity <soft_reset> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/baud.vhd" in
Library uart_plb_v1_00_a.
Entity <baudrate> compiled.
Entity <baudrate> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/tx.vhd" in
Library uart_plb_v1_00_a.
Entity <xmt> compiled.
Entity <xmt> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/fifo_generator_v8_1_8x16.vhd" in
Library uart_plb_v1_00_a.
Entity <fifo_generator_v8_1_8x16> compiled.
Entity <fifo_generator_v8_1_8x16> (Architecture <fifo_generator_v8_1_8x16_a>)
compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/tmo.vhd" in
Library uart_plb_v1_00_a.
Entity <tmo> compiled.
Entity <tmo> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/rx.vhd" in
Library uart_plb_v1_00_a.
Entity <rcv> compiled.
Entity <rcv> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart.vhd" in
Library uart_plb_v1_00_a.
Entity <uart> compiled.
Entity <uart> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_0
1_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.
Entity <interrupt_control> compiled.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plbv46_slave_single> compiled.
Entity <plbv46_slave_single> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/user_logic.vhd" in Library
uart_plb_v1_00_a.
Entity <user_logic> compiled.
Entity <user_logic> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_plb.vhd"
in Library uart_plb_v1_00_a.
Entity <uart_plb> compiled.
ERROR:HDLParsers:851 -
   "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_plb.vhd" Line 476. Formal
   rx_sin of entity with no default value must be associated with an actual
   value.
ERROR:EDK:2121 - Parse Errors encountered in HDL source
WARNING:EDK:3590 - Unable to delete temporary project file
   C:\uart_plb\pcores\uart_plb.prj : 13
HDL language for the peripheral (top level) design unit uart_plb is vhdl ...
WARNING:EDK:2221 - Project file C:\uart_plb\pcores/uart_plb.prj already exists,
   will be overwrite and removed afterward ...
resolving hierarchical inclusion of library proc_common_v3_00_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
resolving hierarchical inclusion of library plbv46_slave_single_v1_01_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
resolving hierarchical inclusion of library interrupt_control_v2_01_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
INFO:EDK:3391 - Create temporary xst project file:
   C:\uart_plb\pcores/uart_plb.prj
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/inferred_lut4.vhd" in Library proc_common_v3_00_a.
Entity <inferred_lut4> compiled.
Entity <inferred_lut4> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/muxf_struct_f.vhd" in Library proc_common_v3_00_a.
Entity <muxf_struct> compiled.
Entity <muxf_struct> (Architecture <imp>) compiled.
Entity <muxf_struct_f> compiled.
Entity <muxf_struct_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_bit> compiled.
Entity <pf_counter_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/cntr_incr_decr_addn_f.vhd" in Library proc_common_v3_00_a.
Entity <cntr_incr_decr_addn_f> compiled.
Entity <cntr_incr_decr_addn_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/dynshreg_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_f> compiled.
Entity <dynshreg_f> (Architecture <behavioral>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_adder_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder_bit> compiled.
Entity <pf_adder_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter> compiled.
Entity <pf_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_occ_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter> compiled.
Entity <pf_occ_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <counter_bit> compiled.
Entity <counter_bit> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy_f.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy_f> compiled.
Entity <or_muxcy_f> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_rbu_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu_f> compiled.
Entity <srl_fifo_rbu_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family.vhd" in Library proc_common_v3_00_a.
Package <family> compiled.
Package body <family> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_occ_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter_top> compiled.
Entity <pf_occ_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_top> compiled.
Entity <pf_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_adder.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder> compiled.
Entity <pf_adder> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter.vhd" in Library proc_common_v3_00_a.
Entity <Counter> compiled.
Entity <Counter> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/coregen_comp_defs.vhd" in Library proc_common_v3_00_a.
Package <coregen_comp_defs> compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_components.vhd" in Library
uart_plb_v1_00_a.
Package <uart_components> compiled.
Package body <uart_components> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/common_types_pkg.vhd" in Library proc_common_v3_00_a.
Package <Common_Types> compiled.
Package body <Common_Types> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/conv_funs_pkg.vhd" in Library proc_common_v3_00_a.
Package <conv_funs_pkg> compiled.
Package body <conv_funs_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/async_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <async_fifo_fg> compiled.
Entity <async_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/sync_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <sync_fifo_fg> compiled.
Entity <sync_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/blk_mem_gen_wrapper.vhd" in Library proc_common_v3_00_a.
Entity <blk_mem_gen_wrapper> compiled.
Entity <blk_mem_gen_wrapper> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/addsub.vhd" in Library proc_common_v3_00_a.
Entity <addsub> compiled.
Entity <addsub> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/direct_path_cntr.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr> compiled.
Entity <direct_path_cntr> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/direct_path_cntr_ai.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr_ai> compiled.
Entity <direct_path_cntr_ai> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/down_counter.vhd" in Library proc_common_v3_00_a.
Entity <down_counter> compiled.
Entity <down_counter> (Architecture <simulation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/eval_timer.vhd" in Library proc_common_v3_00_a.
Entity <eval_timer> compiled.
Entity <eval_timer> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_steer.vhd" in Library proc_common_v3_00_a.
Entity <IPIF_Steer> compiled.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_steer128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_steer128> compiled.
Entity <ipif_steer128> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_mirror128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_mirror128> compiled.
Entity <ipif_mirror128> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ld_arith_reg.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg> compiled.
Entity <ld_arith_reg> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ld_arith_reg2.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg2> compiled.
Entity <ld_arith_reg2> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/mux_onehot.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot> compiled.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_bits.vhd" in Library proc_common_v3_00_a.
Entity <or_bits> compiled.
Entity <or_bits> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate.vhd" in Library proc_common_v3_00_a.
Entity <or_gate> compiled.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_dpram_select.vhd" in Library proc_common_v3_00_a.
Entity <pf_dpram_select> compiled.
Entity <pf_dpram_select> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect.vhd" in Library proc_common_v3_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_mask.vhd" in Library proc_common_v3_00_a.
Entity <pselect_mask> compiled.
Entity <pselect_mask> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl16_fifo.vhd" in Library proc_common_v3_00_a.
Entity <srl16_fifo> compiled.
Entity <srl16_fifo> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo.vhd" in Library proc_common_v3_00_a.
Entity <SRL_FIFO> compiled.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo2.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo2> compiled.
Entity <srl_fifo2> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo3.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo3> compiled.
Entity <srl_fifo3> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_rbu.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu> compiled.
Entity <srl_fifo_rbu> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/valid_be.vhd" in Library proc_common_v3_00_a.
Entity <valid_be> compiled.
Entity <valid_be> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_with_enable_f.vhd" in Library proc_common_v3_00_a.
Entity <or_with_enable_f> compiled.
Entity <or_with_enable_f> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/dynshreg_i_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_i_f> compiled.
Entity <dynshreg_i_f> (Architecture <behavioral>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/mux_onehot_f.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot_f> compiled.
Entity <mux_onehot_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_f> compiled.
Entity <srl_fifo_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/compare_vectors_f.vhd" in Library proc_common_v3_00_a.
Entity <compare_vectors_f> compiled.
Entity <compare_vectors_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate_f.vhd" in Library proc_common_v3_00_a.
Entity <or_gate_f> compiled.
Entity <or_gate_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/soft_reset.vhd" in Library proc_common_v3_00_a.
Entity <soft_reset> compiled.
Entity <soft_reset> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/baud.vhd" in
Library uart_plb_v1_00_a.
Entity <baudrate> compiled.
Entity <baudrate> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/tx.vhd" in
Library uart_plb_v1_00_a.
Entity <xmt> compiled.
Entity <xmt> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/fifo_generator_v8_1_8x16.vhd" in
Library uart_plb_v1_00_a.
Entity <fifo_generator_v8_1_8x16> compiled.
Entity <fifo_generator_v8_1_8x16> (Architecture <fifo_generator_v8_1_8x16_a>)
compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/tmo.vhd" in
Library uart_plb_v1_00_a.
Entity <tmo> compiled.
Entity <tmo> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/rx.vhd" in
Library uart_plb_v1_00_a.
Entity <rcv> compiled.
Entity <rcv> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart.vhd" in
Library uart_plb_v1_00_a.
Entity <uart> compiled.
Entity <uart> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_0
1_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.
Entity <interrupt_control> compiled.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plbv46_slave_single> compiled.
Entity <plbv46_slave_single> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/user_logic.vhd" in Library
uart_plb_v1_00_a.
Entity <user_logic> compiled.
Entity <user_logic> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_plb.vhd"
in Library uart_plb_v1_00_a.
Entity <uart_plb> compiled.
ERROR:HDLParsers:3312 -
   "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_plb.vhd" Line 490.
   Undefined symbol 'tx_sout'.
ERROR:HDLParsers:1209 -
   "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_plb.vhd" Line 490.
   tx_sout: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 -
   "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_plb.vhd" Line 491.
   Undefined symbol 'rx_sin'.
ERROR:HDLParsers:1209 -
   "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_plb.vhd" Line 491. rx_sin:
   Undefined symbol (last report in this block)
ERROR:HDLParsers:851 -
   "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_plb.vhd" Line 476. Formal
   rx_sin of entity with no default value must be associated with an actual
   value.
ERROR:EDK:2121 - Parse Errors encountered in HDL source
WARNING:EDK:3590 - Unable to delete temporary project file
   C:\uart_plb\pcores\uart_plb.prj : 13
HDL language for the peripheral (top level) design unit uart_plb is vhdl ...
WARNING:EDK:2221 - Project file C:\uart_plb\pcores/uart_plb.prj already exists,
   will be overwrite and removed afterward ...
resolving hierarchical inclusion of library proc_common_v3_00_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
resolving hierarchical inclusion of library plbv46_slave_single_v1_01_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
resolving hierarchical inclusion of library interrupt_control_v2_01_a in
C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/ ...
INFO:EDK:3391 - Create temporary xst project file:
   C:\uart_plb\pcores/uart_plb.prj
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/inferred_lut4.vhd" in Library proc_common_v3_00_a.
Entity <inferred_lut4> compiled.
Entity <inferred_lut4> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/muxf_struct_f.vhd" in Library proc_common_v3_00_a.
Entity <muxf_struct> compiled.
Entity <muxf_struct> (Architecture <imp>) compiled.
Entity <muxf_struct_f> compiled.
Entity <muxf_struct_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_bit> compiled.
Entity <pf_counter_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/cntr_incr_decr_addn_f.vhd" in Library proc_common_v3_00_a.
Entity <cntr_incr_decr_addn_f> compiled.
Entity <cntr_incr_decr_addn_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/dynshreg_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_f> compiled.
Entity <dynshreg_f> (Architecture <behavioral>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_adder_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder_bit> compiled.
Entity <pf_adder_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter> compiled.
Entity <pf_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_occ_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter> compiled.
Entity <pf_occ_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <counter_bit> compiled.
Entity <counter_bit> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy_f.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy_f> compiled.
Entity <or_muxcy_f> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_rbu_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu_f> compiled.
Entity <srl_fifo_rbu_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family.vhd" in Library proc_common_v3_00_a.
Package <family> compiled.
Package body <family> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_occ_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter_top> compiled.
Entity <pf_occ_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_top> compiled.
Entity <pf_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_adder.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder> compiled.
Entity <pf_adder> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter.vhd" in Library proc_common_v3_00_a.
Entity <Counter> compiled.
Entity <Counter> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/coregen_comp_defs.vhd" in Library proc_common_v3_00_a.
Package <coregen_comp_defs> compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_components.vhd" in Library
uart_plb_v1_00_a.
Package <uart_components> compiled.
Package body <uart_components> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/common_types_pkg.vhd" in Library proc_common_v3_00_a.
Package <Common_Types> compiled.
Package body <Common_Types> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/conv_funs_pkg.vhd" in Library proc_common_v3_00_a.
Package <conv_funs_pkg> compiled.
Package body <conv_funs_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/async_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <async_fifo_fg> compiled.
Entity <async_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/sync_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <sync_fifo_fg> compiled.
Entity <sync_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/blk_mem_gen_wrapper.vhd" in Library proc_common_v3_00_a.
Entity <blk_mem_gen_wrapper> compiled.
Entity <blk_mem_gen_wrapper> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/addsub.vhd" in Library proc_common_v3_00_a.
Entity <addsub> compiled.
Entity <addsub> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/direct_path_cntr.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr> compiled.
Entity <direct_path_cntr> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/direct_path_cntr_ai.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr_ai> compiled.
Entity <direct_path_cntr_ai> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/down_counter.vhd" in Library proc_common_v3_00_a.
Entity <down_counter> compiled.
Entity <down_counter> (Architecture <simulation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/eval_timer.vhd" in Library proc_common_v3_00_a.
Entity <eval_timer> compiled.
Entity <eval_timer> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_steer.vhd" in Library proc_common_v3_00_a.
Entity <IPIF_Steer> compiled.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_steer128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_steer128> compiled.
Entity <ipif_steer128> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_mirror128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_mirror128> compiled.
Entity <ipif_mirror128> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ld_arith_reg.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg> compiled.
Entity <ld_arith_reg> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ld_arith_reg2.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg2> compiled.
Entity <ld_arith_reg2> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/mux_onehot.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot> compiled.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_bits.vhd" in Library proc_common_v3_00_a.
Entity <or_bits> compiled.
Entity <or_bits> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate.vhd" in Library proc_common_v3_00_a.
Entity <or_gate> compiled.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pf_dpram_select.vhd" in Library proc_common_v3_00_a.
Entity <pf_dpram_select> compiled.
Entity <pf_dpram_select> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect.vhd" in Library proc_common_v3_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_mask.vhd" in Library proc_common_v3_00_a.
Entity <pselect_mask> compiled.
Entity <pselect_mask> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl16_fifo.vhd" in Library proc_common_v3_00_a.
Entity <srl16_fifo> compiled.
Entity <srl16_fifo> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo.vhd" in Library proc_common_v3_00_a.
Entity <SRL_FIFO> compiled.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo2.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo2> compiled.
Entity <srl_fifo2> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo3.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo3> compiled.
Entity <srl_fifo3> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_rbu.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu> compiled.
Entity <srl_fifo_rbu> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/valid_be.vhd" in Library proc_common_v3_00_a.
Entity <valid_be> compiled.
Entity <valid_be> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_with_enable_f.vhd" in Library proc_common_v3_00_a.
Entity <or_with_enable_f> compiled.
Entity <or_with_enable_f> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/dynshreg_i_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_i_f> compiled.
Entity <dynshreg_i_f> (Architecture <behavioral>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/mux_onehot_f.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot_f> compiled.
Entity <mux_onehot_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/srl_fifo_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_f> compiled.
Entity <srl_fifo_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/compare_vectors_f.vhd" in Library proc_common_v3_00_a.
Entity <compare_vectors_f> compiled.
Entity <compare_vectors_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate_f.vhd" in Library proc_common_v3_00_a.
Entity <or_gate_f> compiled.
Entity <or_gate_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/soft_reset.vhd" in Library proc_common_v3_00_a.
Entity <soft_reset> compiled.
Entity <soft_reset> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/baud.vhd" in
Library uart_plb_v1_00_a.
Entity <baudrate> compiled.
Entity <baudrate> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/tx.vhd" in
Library uart_plb_v1_00_a.
Entity <xmt> compiled.
Entity <xmt> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/fifo_generator_v8_1_8x16.vhd" in
Library uart_plb_v1_00_a.
Entity <fifo_generator_v8_1_8x16> compiled.
Entity <fifo_generator_v8_1_8x16> (Architecture <fifo_generator_v8_1_8x16_a>)
compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/tmo.vhd" in
Library uart_plb_v1_00_a.
Entity <tmo> compiled.
Entity <tmo> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/rx.vhd" in
Library uart_plb_v1_00_a.
Entity <rcv> compiled.
Entity <rcv> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart.vhd" in
Library uart_plb_v1_00_a.
Entity <uart> compiled.
Entity <uart> (Architecture <rtl>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_0
1_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.
Entity <interrupt_control> compiled.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plbv46_slave_single> compiled.
Entity <plbv46_slave_single> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/user_logic.vhd" in Library
uart_plb_v1_00_a.
Entity <user_logic> compiled.
Entity <user_logic> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/uart_plb/pcores/uart_plb_v1_00_a/hdl/vhdl/uart_plb.vhd"
in Library uart_plb_v1_00_a.
Entity <uart_plb> compiled.
Entity <uart_plb> (Architecture <IMP>) compiled.


Analyzing HDL attributes ...
Entity name = uart_plb
INFO:EDK:1607 - IPTYPE set to value : PERIPHERAL
INFO:EDK:1511 - IMP_NETLIST set to value : TRUE
INFO:EDK:1486 - HDL set to value : VHDL
WARNING:EDK:3590 - Unable to delete temporary project file
   C:\uart_plb\pcores\uart_plb.prj : 13
WARNING:EDK:2140 - Peripheral name mismatch, no MPD merge will be processed!

WARNING:EDK:2065 - PARAMETER:_NUM_SLAVES - SLAVE PLBV46 parameter is not defined
   in the HDL source
INFO:EDK:1631 - Infer bus clock [SPLB_Clk] for bus interface SPLB ...
Copying file uart_components.vhd to
C:\uart_plb\pcores/uart_plb_v1_00_a/hdl/vhdl/ ...
Copying file baud.vhd to C:\uart_plb\pcores/uart_plb_v1_00_a/hdl/vhdl/ ...
Copying file tmo.vhd to C:\uart_plb\pcores/uart_plb_v1_00_a/hdl/vhdl/ ...
Copying file fifo_generator_v8_1_8x16.vhd to
C:\uart_plb\pcores/uart_plb_v1_00_a/hdl/vhdl/ ...
Copying file rx.vhd to C:\uart_plb\pcores/uart_plb_v1_00_a/hdl/vhdl/ ...
Copying file tx.vhd to C:\uart_plb\pcores/uart_plb_v1_00_a/hdl/vhdl/ ...
Copying file uart.vhd to C:\uart_plb\pcores/uart_plb_v1_00_a/hdl/vhdl/ ...
Copying file user_logic.vhd to C:\uart_plb\pcores/uart_plb_v1_00_a/hdl/vhdl/ ...
Copying file uart_plb.vhd to C:\uart_plb\pcores/uart_plb_v1_00_a/hdl/vhdl/ ...

Thank you for using Create and Import Peripheral Wizard! Please find your
imported peripheral under C:\uart_plb\pcores\uart_plb_v1_00_a.

Summary:

  Logical library     : uart_plb_v1_00_a
  Version             : 1.00.a
  Bus interface(s)    : SPLB 

The following sub-directories will be created:

  - uart_plb_v1_00_a\data
  - uart_plb_v1_00_a\doc
  - uart_plb_v1_00_a\hdl
  - uart_plb_v1_00_a\hdl\vhdl
  - uart_plb_v1_00_a\netlist


The following HDL source files will be copied into the uart_plb_v1_00_a\hdl\vhdl
directory:

  - uart_components.vhd
  - baud.vhd
  - tmo.vhd
  - fifo_generator_v8_1_8x16.vhd
  - rx.vhd
  - tx.vhd
  - uart.vhd
  - user_logic.vhd
  - uart_plb.vhd

The following files will be created under the uart_plb_v1_00_a\data directory:

  - uart_plb_v2_1_0.mpd
  - uart_plb_v2_1_0.pao

  - uart_plb_v2_1_0.bbd

The following netlist file(s) will be copied into the uart_plb_v1_00_a\netlist
directory:

  - fifo_generator_v8_1_8x16.ngc

The following document file(s) will be copied into the uart_plb_v1_00_a\doc
directory:

  - readme.txt