Subversion Repositories udp_ip_stack

CONFIG PART = xc6vlx240tff1156-1;


########## ML605 Board ##########
NET  clk_in_p        LOC = J9   |IOSTANDARD = LVDS_25  |DIFF_TERM = TRUE;
NET  clk_in_n        LOC = H9   |IOSTANDARD = LVDS_25  |DIFF_TERM = TRUE;

Net reset         LOC = H10  |IOSTANDARD = LVCMOS15 |TIG;

# downgrade the Place:1153 error in the mapper
NET "reset" CLOCK_DEDICATED_ROUTE = FALSE;

#### Module LEDs_8Bit constraints
NET "display[0]" LOC = AC22;
NET "display[1]" LOC = AC24;
NET "display[2]" LOC = AE22;
NET "display[3]" LOC = AE23;
NET "display[4]" LOC = AB23;
NET "display[5]" LOC = AG23;
NET "display[6]" LOC = AE24;
NET "display[7]" LOC = AD24;

NET PBTX_LED                            LOC = AD21;
NET UDP_RX                              LOC = AH27;
NET DO_SECOND_TX_LED    LOC = AH28;
NET TX_RSLT_0                   LOC = AE21;
NET TX_RSLT_1                   LOC = AP24;



#### Module Push_Buttons_4Bit constraints
NET PBTX                                                LOC = H17;
NET PB_DO_SECOND_TX             LOC = A18;
NET reset_leds                          LOC = G26;

#### Module DIP_Switches_4Bit constraints


Net phy_resetn       LOC = AH13 |IOSTANDARD = LVCMOS25 |TIG;

Net gmii_rxd<7>      LOC = AC13 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<6>      LOC = AC12 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<5>      LOC = AD11 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<4>      LOC = AM12 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<3>      LOC = AN12 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<2>      LOC = AE14 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<1>      LOC = AF14 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<0>      LOC = AN13 |IOSTANDARD = LVCMOS25;

Net gmii_txd<7>      LOC = AF11 |IOSTANDARD = LVCMOS25;
Net gmii_txd<6>      LOC = AE11 |IOSTANDARD = LVCMOS25;
Net gmii_txd<5>      LOC = AM10 |IOSTANDARD = LVCMOS25;
Net gmii_txd<4>      LOC = AL10 |IOSTANDARD = LVCMOS25;
Net gmii_txd<3>      LOC = AG11 |IOSTANDARD = LVCMOS25;
Net gmii_txd<2>      LOC = AG10 |IOSTANDARD = LVCMOS25;
Net gmii_txd<1>      LOC = AL11 |IOSTANDARD = LVCMOS25;
Net gmii_txd<0>      LOC = AM11 |IOSTANDARD = LVCMOS25;

Net gmii_col         LOC = AK13 |IOSTANDARD = LVCMOS25;
Net gmii_crs         LOC = AL13 |IOSTANDARD = LVCMOS25;
Net mii_tx_clk       LOC = AD12 |IOSTANDARD = LVCMOS25;

Net gmii_tx_en       LOC = AJ10 |IOSTANDARD = LVCMOS25;
Net gmii_tx_er       LOC = AH10 |IOSTANDARD = LVCMOS25;
Net gmii_tx_clk      LOC = AH12 |IOSTANDARD = LVCMOS25;

Net gmii_rx_dv       LOC = AM13 |IOSTANDARD = LVCMOS25;
Net gmii_rx_er       LOC = AG12 |IOSTANDARD = LVCMOS25;
# P20 - GCLK7 
Net gmii_rx_clk      LOC = AP11 |IOSTANDARD = LVCMOS25;



NET "clk_in_p" TNM_NET = "clk_in_p";
TIMESPEC "TS_emac1_clk_in_p" = PERIOD "clk_in_p" 5.000 ns HIGH 50% INPUT_JITTER 50.0ps;


# Ethernet GTX_CLK high quality 125 MHz reference clock
NET "*mac_block/gtx_clk_bufg" TNM_NET = "ref_gtx_clk";
TIMEGRP "v6_emac_v2_1_clk_ref_gtx" = "ref_gtx_clk";
TIMESPEC "TS_v6_emac_v2_1_clk_ref_gtx" = PERIOD "v6_emac_v2_1_clk_ref_gtx" 8 ns HIGH 50 %;

# Multiplexed 1 Gbps, 10/100 Mbps output inherits constraint from GTX_CLK
NET "*tx_mac_aclk*" TNM_NET  = "clk_tx_mac";
TIMEGRP "v6_emac_v2_1_clk_ref_mux" = "clk_tx_mac";
TIMESPEC "TS_v6_emac_v2_1_clk_ref_mux" = PERIOD "v6_emac_v2_1_clk_ref_mux" TS_v6_emac_v2_1_clk_ref_gtx HIGH 50%;

# Ethernet GMII PHY-side receive clock
NET "gmii_rx_clk" TNM_NET = "phy_clk_rx";
TIMEGRP "v6_emac_v2_1_clk_phy_rx" = "phy_clk_rx";
TIMESPEC "TS_v6_emac_v2_1_clk_phy_rx" = PERIOD "v6_emac_v2_1_clk_phy_rx" 7.5 ns HIGH 50 %;

# define TIGs between unrelated clock domains
TIMESPEC "TS_clock_path_gtx2ref" = FROM "clock_generator_clkout0" TO "clock_generator_clkout2" TIG;
PIN "*bufgmux_speed_clk.I1" TIG;
PIN "*bufgmux_speed_clk.CE0" TIG;

#
####
#######
##########
#############
#################
#FIFO BLOCK CONSTRAINTS

# Group design elements around the Ethernet MAC to assist with timing
# closure in this example design. These values may be modified or
# removed to best suit your design.
#INST "*user_side_FIFO?tx_fifo_i?ramgen_l?bram18_tdp_bl?bram18_tdp_bl" LOC = "RAMB36_X6Y34";
#INST "*user_side_FIFO?rx_fifo_i?ramgen_l?bram18_tdp_bl?bram18_tdp_bl" LOC = "RAMB36_X6Y35";
#INST "*user_side_FIFO?tx_fifo_i?ramgen_u?bram18_tdp_bl?bram18_tdp_bl" LOC = "RAMB36_X6Y36";
#INST "*user_side_FIFO?rx_fifo_i?ramgen_u?bram18_tdp_bl?bram18_tdp_bl" LOC = "RAMB36_X6Y37";

###############################################################################
# AXI FIFO CONSTRAINTS
# The following constraints are necessary for proper operation of the AXI
# FIFO. If you choose to not use the FIFO Block level of wrapper hierarchy,
# these constraints should be removed.
###############################################################################

# AXI FIFO transmit-side constraints
# -----------------------------------------------------------------------------

# Group the clock crossing signals into timing groups
INST "*user_side_FIFO?tx_fifo_i?rd_tran_frame_tog"    TNM = "tx_fifo_rd_to_wr";
INST "*user_side_FIFO?tx_fifo_i?rd_retran_frame_tog"  TNM = "tx_fifo_rd_to_wr";
INST "*user_side_FIFO?tx_fifo_i?rd_col_window_pipe_1" TNM = "tx_fifo_rd_to_wr";
INST "*user_side_FIFO?tx_fifo_i?rd_addr_txfer*"       TNM = "tx_fifo_rd_to_wr";
INST "*user_side_FIFO?tx_fifo_i?rd_txfer_tog"         TNM = "tx_fifo_rd_to_wr";
INST "*user_side_FIFO?tx_fifo_i?wr_frame_in_fifo"     TNM = "tx_fifo_wr_to_rd";

TIMESPEC "TS_tx_fifo_rd_to_wr" = FROM "tx_fifo_rd_to_wr" TO "v6_emac_v2_1_clk_ref_mux" 8 ns DATAPATHONLY;
TIMESPEC "TS_tx_fifo_wr_to_rd" = FROM "tx_fifo_wr_to_rd" TO "v6_emac_v2_1_clk_ref_mux" 8 ns DATAPATHONLY;

# Reduce clock period to allow for metastability settling time
INST "*user_side_FIFO?tx_fifo_i?wr_rd_addr*"          TNM = "tx_metastable";
INST "*user_side_FIFO?tx_fifo_i?wr_col_window_pipe_0" TNM = "tx_metastable";
TIMESPEC "TS_tx_meta_protect" = FROM "tx_metastable" 5 ns DATAPATHONLY;

# Transmit-side AXI FIFO address bus timing
INST "*user_side_FIFO?tx_fifo_i?rd_addr_txfer*" TNM = "tx_addr_rd";
INST "*user_side_FIFO?tx_fifo_i?wr_rd_addr*"    TNM = "tx_addr_wr";
TIMESPEC "TS_tx_fifo_addr" = FROM "tx_addr_rd" TO "tx_addr_wr" 10 ns;

# AXI FIFO receive-side constraints
# -----------------------------------------------------------------------------

# Group the clock crossing signals into timing groups
INST "*user_side_FIFO?rx_fifo_i?wr_store_frame_tog" TNM = "rx_fifo_wr_to_rd";
INST "*user_side_FIFO?rx_fifo_i?rd_addr*"           TNM = "rx_fifo_rd_to_wr";

TIMESPEC "TS_rx_fifo_wr_to_rd" = FROM "rx_fifo_wr_to_rd" TO "v6_emac_v2_1_clk_ref_mux" 8 ns DATAPATHONLY;
TIMESPEC "TS_rx_fifo_rd_to_wr" = FROM "rx_fifo_rd_to_wr" TO "v6_emac_v2_1_clk_phy_rx"  8 ns DATAPATHONLY;



#
####
#######
##########
#############
#################
#BLOCK CONSTRAINTS

# Locate the Tri-Mode Ethernet MAC instance
INST "*v6_emac" LOC = "TEMAC_X0Y0";


###############################################################################
# PHYSICAL INTERFACE CONSTRAINTS
# The following constraints are necessary for proper operation, and are tuned
# for this example design. They should be modified to suit your design.
###############################################################################

# GMII physical interface constraints
# -----------------------------------------------------------------------------

# Set the IDELAY values on the PHY inputs, tuned for this example design.
# These values should be modified to suit your design.
INST "*v6emac_block*gmii_interface*delay_gmii_rx_dv"    IDELAY_VALUE = 22;
INST "*v6emac_block*gmii_interface*delay_gmii_rx_er"    IDELAY_VALUE = 22;
INST "*v6emac_block*gmii_interface*delay_gmii_rxd"      IDELAY_VALUE = 22;

# Group all IDELAY-related blocks to use a single IDELAYCTRL
INST "*dlyctrl"                                      IODELAY_GROUP = gmii_idelay;
INST "*v6emac_block*gmii_interface*delay_gmii_rx_dv" IODELAY_GROUP = gmii_idelay;
INST "*v6emac_block*gmii_interface*delay_gmii_rx_er" IODELAY_GROUP = gmii_idelay;
INST "*v6emac_block*gmii_interface*delay_gmii_rxd"   IODELAY_GROUP = gmii_idelay;

# The following constraints work in conjunction with IDELAY_VALUE settings to
# check that the GMII receive bus remains in alignment with the rising edge of
# GMII_RX_CLK, to within 2 ns setup time and 750 ps hold time. 
# In addition to adjusting IDELAY_VALUE settings for your system's timing 
# characteristics, you may wish to refine these constraints to match the GMII specification; 
# see Answer Record 33195 on xilinx.com for details.
INST "gmii_rxd<?>" TNM = "gmii_rx";
INST "gmii_rx_dv"  TNM = "gmii_rx";
INST "gmii_rx_er"  TNM = "gmii_rx";
TIMEGRP "gmii_rx" OFFSET = IN 2 ns VALID 2.75 ns BEFORE "gmii_rx_clk" RISING;

# Constrain the GMII physical interface flip-flops to IOBs
INST "*v6emac_block*gmii_interface*rxd_to_mac*"  IOB = force;
INST "*v6emac_block*gmii_interface*rx_dv_to_mac" IOB = force;
INST "*v6emac_block*gmii_interface*rx_er_to_mac" IOB = force;
INST "*v6emac_block*gmii_interface*gmii_txd_?"   IOB = force;
INST "*v6emac_block*gmii_interface*gmii_tx_en"   IOB = force;
INST "*v6emac_block*gmii_interface*gmii_tx_er"   IOB = force;

# Location constraints are chosen for this example design.
# These values should be modified to suit your design.
# * Note that regional clocking imposes certain requirements
#   on the location of the physical interface pins and the TEMAC instance.
#   Please refer to the Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC
#   User Guide for additional details. *

# Locate the GMII physical interface pins
INST "gmii_txd<?>" LOC = "BANK36";
INST "gmii_tx_en"  LOC = "BANK36";
INST "gmii_tx_er"  LOC = "BANK36";
INST "gmii_tx_clk" LOC = "BANK36";
INST "gmii_rxd<?>" LOC = "BANK36";
INST "gmii_rx_dv"  LOC = "BANK36";
INST "gmii_rx_er"  LOC = "BANK36";
INST "gmii_rx_clk" LOC = "BANK36";

# Locate the 125 MHz reference clock buffer
#INST "*BUFGMUX_SPEED_CLK" LOC = "BUFGCTRL_X0Y24";