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#
# Design Specification
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# Author: Rudolf Usselmann
#         rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
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# ==============================================
# Setup Design Parameters

set design_files {usbf_crc5 usbf_crc16 usbf_mem_arb usbf_ep_rf usbf_pa usbf_ep_rf_dummy usbf_pd usbf_rf usbf_utmi_ls usbf_utmi_if usbf_idma usbf_pe usbf_wb usbf_pl usbf_top}
set design_name usbf_top
set active_design usbf_top

# Next Statement defines all clocks and resets in the design
set special_net {rst_i clk_i phy_clk}

# Source Directory
set hdl_src_dir ../../rtl/verilog/